SLUSD31F October   2018  – July 2026 UCC23513

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Function
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristics Curves
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay, Rise Time and Fall Time
    2. 6.2 IOH and IOL testing
    3. 6.3 CMTI Testing
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supply
      2. 7.3.2 Input Stage
      3. 7.3.3 Output Stage
      4. 7.3.4 Protection Features
        1. 7.3.4.1 Undervoltage Lockout (UVLO)
        2. 7.3.4.2 Active Pulldown
        3. 7.3.4.3 Short-Circuit Clamping
    4. 7.4 Device Functional Modes
      1. 7.4.1 ESD Structure
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selecting the Input Resistor
        2. 8.2.2.2 Gate Driver Output Resistor
        3. 8.2.2.3 Estimate Gate-Driver Power Loss
          1. 8.2.2.3.1 Case 1 - Linear Pull-Up and Pull-Down Resistor
          2. 8.2.2.3.2 Case 2 - Nonlinear pull-up and pull-down Resistor
        4. 8.2.2.4 Estimating Junction Temperature
        5. 8.2.2.5 Selecting VCC Capacitor
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 PCB Material
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.3 Estimate Gate-Driver Power Loss

The total loss, PG, in the gate-driver subsystem includes the power losses (PGD) of the UCC23513 device and the power losses in the peripheral circuitry, such as the external gate-drive resistor.

The PGD value is the key power loss which determines the thermal safety-related limits of the UCC23513 device. Estimate the PGD value by calculating losses from several components.

The first component is the static power loss, PGDQ, which includes power dissipated in the input stage (PGDQ_IN) as well as the quiescent power dissipated in the output stage (PGDQ_OUT) when operating with a certain switching frequency under no load. Determine PGDQ_IN by IF and VF and is given by Equation 5. The PGDQ_OUT parameter is measured on the bench with no load connected to VOUT pin at a given VCC, switching frequency, and ambient temperature. In this example, VCC is 15V. The measurement of current on the power supply, with PWM switching at 10kHz, is ICC = 1.33mA. Therefore, use Equation 6 to calculate PGDQ_OUT.

Equation 5. P G D Q _ I N = 1 2 × V F × I F
Equation 6. P G D Q _ O U T = V C C × I C C

The total quiescent power (without any load capacitance) dissipated in the gate driver is the sum of Equation 5 and Equation 6 as Equation 7 shows.

Equation 7. P G D Q = P G D Q _ I N + P G D Q _ O U T = 10 m W + 20 m W = 30 m W

The second component is the switching operation loss, PGDSW, with a given load capacitance which the driver charges and discharges the load during each switching cycle. Use Equation 8 to calculate the total dynamic loss from load switching, PGSW.

Equation 8. P G S W = V C C 2 × Q G × f S W

where

  • QG is the gate charge of the power transistor at VCC.

So, for this example application the total dynamic loss from load switching is approximately 18mW as calculated in Equation 9.

Equation 9. P G S W = 15 V × 120 n C × 10 k H z = 18 m W

QG represents the total gate charge of the power transistor switching 520V at 50A, and is subject to change with different testing conditions. The UCC23513 gate-driver loss on the output stage, PGDO, is part of PGSW. PGDO is equal to PGSW if the external gate-driver resistance and power-transistor internal resistance are 0Ω, and all the gate driver-loss dissipates inside the UCC23513. If an external turn-on and turn-off resistance exists, the total loss is distributed between the gate driver pull-up and pull-down resistance, external gate resistance, and power-transistor internal resistance. Importantly, the pull-up and pull-down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4.5A/5.3A, however, it is nonlinear if the source/sink current is saturated. Therefore, PGDO is different in these two scenarios.