SLUSES3A October   2023  – December 2023 UCC25660

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Power Proportional Control
        1. 7.3.1.1 Voltage Feedforward
      2. 7.3.2 VCR Synthesizer
      3. 7.3.3 Feedback Chain (Control Input)
      4. 7.3.4 Adaptive Dead-Time
      5. 7.3.5 Input Voltage Sensing
        1. 7.3.5.1 Brown in and Brown out Tresholds and Options
        2. 7.3.5.2 Output OVP and External OTP
      6. 7.3.6 Resonant Tank Current Sensing
    4. 7.4 Protections
      1. 7.4.1 Zero Current Switching (ZCS) Protection
      2. 7.4.2 Minimum Current Turn-off During Soft Start
      3. 7.4.3 Cycle by Cycle Current Limit and Short Circuit Protection
      4. 7.4.4 Overload (OLP) Protection
      5. 7.4.5 VCC OVP Protection
    5. 7.5 Device Functional Modes
      1. 7.5.1 Startup
        1. 7.5.1.1 With HV Startup
        2. 7.5.1.2 Without HV Startup
      2. 7.5.2 Soft Start Ramp
        1. 7.5.2.1 Startup Transition to Regulation
      3. 7.5.3 Light Load Management
        1. 7.5.3.1 Operating Modes (Burst Pattern)
        2. 7.5.3.2 Mode Transition Management
        3. 7.5.3.3 Burst Mode Threshold Programming
        4. 7.5.3.4 PFC On/Off
      4. 7.5.4 X-Capacitor Discharge
        1. 7.5.4.1 Detecting Through HV Pin Only
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  LLC Power Stage Requirements
        2. 8.2.2.2  LLC Gain Range
        3. 8.2.2.3  Select Ln and Qe
        4. 8.2.2.4  Determine Equivalent Load Resistance
        5. 8.2.2.5  Determine Component Parameters for LLC Resonant Circuit
        6. 8.2.2.6  LLC Primary-Side Currents
        7. 8.2.2.7  LLC Secondary-Side Currents
        8. 8.2.2.8  LLC Transformer
        9. 8.2.2.9  LLC Resonant Inductor
        10. 8.2.2.10 LLC Resonant Capacitor
        11. 8.2.2.11 LLC Primary-Side MOSFETs
        12. 8.2.2.12 Design Considerations for Adaptive Dead-Time
        13. 8.2.2.13 LLC Rectifier Diodes
        14. 8.2.2.14 LLC Output Capacitors
        15. 8.2.2.15 HV Pin Series Resistors
        16. 8.2.2.16 BLK Pin Voltage Divider
        17. 8.2.2.17 ISNS Pin Differentiator
        18. 8.2.2.18 TSET Pin
        19. 8.2.2.19 OVP/OTP Pin
        20. 8.2.2.20 Burst Mode Programming
        21. 8.2.2.21 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 VCCP Pin Capacitor
      2. 8.3.2 Boot Capacitor
      3. 8.3.3 V5P Pin Capacitor
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Schematics
        2. 8.4.2.2 Schematics
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.19 OVP/OTP Pin

The OVP/OTP is used for protecting the power stage from over voltage. Also, the same pin is also used for over temperature protection using negative temperature coefficient (NTC) thermistor. As the bias winding voltage is the mirror image of the output voltage through the turns ratio of the transformer, pulling up this pin with a zener diode is a convenient approach to set the OVP on the primary side. In this design, the nominal output voltage is 12V. Both the bias winding and the secondary side winding has 2 turns. Assuming there is a 0.5V drop in the rectifier diodes (Vf) and a further 0.5V drop due to other losses (Vloss), the nominal voltage of the bias winding is given by:

Equation 62. V B i a s W i n d i n g N o m = ( 12 + 0.5 + 0.5 ) ⋅ N a u x N 2 = ( 12 + 0.5 + 0.5 ) ⋅ 2 2 = 13 V

The desired OVP threshold in this design is 140% of the nominal value. The OVP threshold level (VOVPpos) in UC25660 device is 3.5V.

The required voltage rating of the Zener diode is then given by:

Equation 63. V z =(1.4⋅ V out + V drop )⋅ N aux N 2 − V OVPpos =(1.4⋅12+0.5+0.5)⋅ 2 2 −3.5=14.3V

Assume actual voltage rating of Zener used is 15V.

Then actual output voltage at which OVP will be triggered is

Equation 64. V out_ovp =( V z + V OVPpos )⋅ N 2 N aux − V drop =(15+3.5)⋅ 2 2 −1=17.5V=146%⋅ V out

During normal operation, the voltage of the OVP/OTP pin should be within the working window of 0.8V to 3.5V. For over temperature protection, the OVP/OTP pin should be pulled down below OTP threshold of 0.8V.

At room temperature, the OVP/OTP pin voltage is considered as 1.4V. So, at room temperature, the effective resistance value at this pin should be

Equation 65. R O V P / O T P _ 25 = 1.4 V I O V P _ O T P = 1.4 V 100 ⋅ 10 − 6 A = 14 k Ω

Equation 66. R O V P / O T P _ 25 = R e x t ⋅ R N T C _ 25 R e x t + R N T C _ 25 = 14 k Ω

where Rext is external resistor that is in parallel with the thermistor. And RNTC_25 is resistance value of the thermistor at the room temperature.

For this design, over temperature protection is set at the 1100C. So based on the availability and temperature coefficient of NTCs,

Equation 67. R N T C _ 110 R N T C _ 25 = 0.035263
(refer B57371V2474J060 Datasheet) is chosen. Here RNTC_110 is the resistance of the thermistor at the 1100C.

For OTP trigger, the OVP/OTP pin voltage should be below 0.8V.

Equation 68. R O V P / O T P _ 110 = 0.8 V I O V P _ O T P = 0.8 V 100 ⋅ 10 − 6 A = 8 k Ω
Equation 69. R O V P / O T P _ 110 = R e x t ⋅ R N T C _ 110 R e x t + R N T C _ 110 = 8 k Ω

From equations,Equation 66, Equation 67, Equation 69, RNTC_25 and Rext are obtained as 510kΩ and 14.4kΩ. So, finally RNTC_25=470kΩ (Manfacturer part number: B57371V2474J060 ) and Rext=15kΩ are chosen.

So, at room temperature, with new chosen resistors, the OVP/OTP voltage will be

Equation 70. R O V P / O T P _ 25 ⋅ I O V P _ O T P = 15 k ⋅ 470 k 15 k + 470 k ⋅ 100 ⋅ 10 − 6 = 1.454 V

At 1100C, the OVP/OTP voltage will be

Equation 71. R O V P / O T P _ 110 ⋅ I O V P _ O T P = 15 k ⋅ ( 470 k ⋅ 0.035263 ) 15 k + ( 470 k ⋅ 0.035263 ) ⋅ 100 ⋅ 10 − 6 = 0.78 V