SLUSBA7G December   2012  – June 2019 UCC27531 , UCC27533 , UCC27536 , UCC27537 , UCC27538


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Driving IGBT Without Negative Bias
  4. Revision History
    1.     Description (continued)
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 VDD Undervoltage Lockout
      2. 8.3.2 Input Stage
      3. 8.3.3 Enable Function
      4. 8.3.4 Output Stage
    4. 8.4 Device Functional Modes
  9. Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Driving IGBT Without Negative Bias
        1. Design Requirements
        2. Detailed Design Procedure
          1. Input-to-Output Configuration
          2. Input Threshold Type
          3. VDD Bias Supply Voltage
          4. Peak Source and Sink Currents
          5. Enable and Disable Function
          6. Propagation Delay
          7. Power Dissipation
        3. Application Curve
      2. 9.2.2 Driving IGBT With 13-V Negative Turn-Off BIAS
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
      3. 9.2.3 Single-Output Driver
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
      4. 9.2.4 Using UCC2753x Drivers in an Inverter
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Consideration
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Output Stage

The output stage of the UCC2753x device is illustrated in Figure 39. The UCC2753x device features a unique architecture on the output stage which delivers the highest peak source current when it is most needed during the Miller plateau region of the power switch turn-on transition (when the power switch drain/collector voltage experiences dV/dt). The device output stage features a hybrid pull-up structure using a parallel arrangement of N-Channel and P-Channel MOSFET devices. By turning on the N-Channel MOSFET during a narrow instant when the output changes state from low to high, the gate driver device is able to deliver a brief boost in the peak sourcing current enabling fast turnon.

UCC27531 UCC27533 UCC27536 UCC27537 UCC27538 gate_lusba7.gifFigure 39. UCC27531 Gate Driver Output Stage

Split output depicted in Figure 39. For devices with single OUT pin, OUTH and OUTL are connected internally and then connected to OUT.

The ROH parameter (see Electrical Table) is a DC measurement and it is representative of the on-resistance of the P-Channel device only, because the N-Channel device is turned on only during output change of state from low to high. Thus the effective resistance of the hybrid pull-up stage is much lower than what is represented by ROH parameter. The pull-down structure is composed of a N-channel MOSFET only. The ROL parameter (see Electrical Characteristics), which is also a DC measurement, is representative of true impedance of the pull-down stage in the device. In UCC2753x, the effective resistance of the hybrid pull-up structure is approximately 3 x ROL.

The UCC2753x can deliver 2.5-A source, and up to 5-A sink at VDD = 18 V. Strong sink capability results in a very low pull-down impedance in the driver output stage which boosts immunity against the parasitic Miller turn-on (high slew rate dV/dt turnon) effect that is seen in both IGBT and FET power switches .

An example of a situation where Miller turnon is a concern is synchronous rectification (SR). In SR application, the dV/dt occurs on MOSFET drain when the MOSFET is already held in OFF state by the gate driver. The current charging the CGD Miller capacitance during this high dV/dt is shunted by the pull-down stage of the driver. If the pull-down impedance is not low enough then a voltage spike can result in the VGS of the MOSFET, which can result in spurious turnon. This phenomenon is illustrated in Figure 40.

UCC27531 UCC27533 UCC27536 UCC27537 UCC27538 pull_lusba7.gifFigure 40. Low Pull-Down Impedance in UCC2753x
(Output Stage Mitigates Miller Turn-On Effect)

The driver output voltage swings between VDD and GND providing rail-to-rail operation because of the low dropout of the output stage. In many cases, the external Schottky diode clamps may be eliminated because the presence of the MOSFET body diodes offers low impedance to switching overshoots and undershoots.