SLUSCE9B June   2017  – March 2020 UCC27712

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Typical Propagation Delay Comparison
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Dynamic Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD and Under Voltage Lockout
      2. 7.3.2 Input and Output Logic Table
      3. 7.3.3 Input Stage
      4. 7.3.4 Output Stage
      5. 7.3.5 Level Shift
      6. 7.3.6 Low Propagation Delays and Tightly Matched Outputs
      7. 7.3.7 Parasitic Diode Structure
    4. 7.4 Device Functional Modes
      1. 7.4.1 Minimum Input Pulse Operation
      2. 7.4.2 Output Interlock and Dead Time
      3. 7.4.3 Operation Under 100% Duty Cycle Condition
      4. 7.4.4 Operation Under Negative HS Voltage Condition
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selecting HI and LI Low Pass Filter Components (RHI, RLI, CHI, CLI)
        2. 8.2.2.2 Selecting Bootstrap Capacitor (CBOOT)
        3. 8.2.2.3 Selecting VDD Bypass/Holdup Capacitor (CVDD) and Rbias
        4. 8.2.2.4 Selecting Bootstrap Resistor (RBOOT)
        5. 8.2.2.5 Selecting Gate Resistor RON/ROFF
        6. 8.2.2.6 Selecting Bootstrap Diode
        7. 8.2.2.7 Estimate the UCC27712 Power Losses (PUCC27712)
        8. 8.2.2.8 Estimating Junction Temperature
        9. 8.2.2.9 Operation With IGBT's
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • High-side and low-side configuration
  • Dual inputs with output interlock and 150-ns deadtime
  • Fully operational up to 620-V, 700-V absolute maximum on HB pin
  • 10-V to 20-V VDD recommended range
  • Peak output current 2.8-A sink, 1.8-A source
  • dv/dt immunity of 50 V/ns
  • Logic operational up to –11 V on HS pin
  • Negative voltage tolerance on inputs of –5 V
  • Large negative transient safe operating area
  • UVLO protection for both channels
  • Small propagation delay (100-ns typical)
  • Delay matching (12-ns typical)
  • Floating channel designed for bootstrap operation
  • Low quiescent current
  • TTL and CMOS compatible inputs
  • Industry standard SOIC-8 package
  • All parameters specified over temperature range, –40 °C to +125 °C