SLUSC61A January   2015  – December 2020 UCC28700-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings (1)
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Description
        1. 7.3.1.1 VDD (Device Bias Voltage Supply)
        2. 7.3.1.2 GND (Ground)
        3. 7.3.1.3 VS (Voltage-Sense)
        4. 7.3.1.4 DRV (Gate Drive)
        5. 7.3.1.5 CS (Current Sense)
        6. 7.3.1.6 CBC (Cable Compensation)
      2. 7.3.2 Fault Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Primary-Side Voltage Regulation
      2. 7.4.2 Primary-Side Current Regulation
      3. 7.4.3 Valley-Switching
      4. 7.4.4 Start-Up Operation
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Transformer Parameter Verification
        2. 8.2.2.2 Output Capacitance
        3. 8.2.2.3 VDD Capacitance, CDD
        4. 8.2.2.4 VDD Start-Up Resistance, RSTR
        5. 8.2.2.5 VS Resistor Divider, Line Compensation, and Cable Compensation
        6. 8.2.2.6 Input Bulk Capacitance and Minimum Bulk Voltage
        7. 8.2.2.7 Transformer Turns Ratio, Inductance, Primary-Peak Current
        8. 8.2.2.8 Standby Power Estimate
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1  Capacitance Terms in Farads
        2. 11.1.1.2  Duty Cycle Terms
        3. 11.1.1.3  Frequency Terms in Hertz
        4. 11.1.1.4  Current Terms in Amperes
        5. 11.1.1.5  Current and Voltage Scaling Terms
        6. 11.1.1.6  Transformer Terms
        7. 11.1.1.7  Power Terms in Watts
        8. 11.1.1.8  Resistance Terms in Ω
        9. 11.1.1.9  Timing Terms in Seconds
        10. 11.1.1.10 Voltage Terms in Volts
        11. 11.1.1.11 AC Voltage Terms in VRMS
        12. 11.1.1.12 Efficiency Terms
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Trademarks

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.4 Start-Up Operation

Upon application of input voltage to the converter, the start-up resistor connected to VDD from the bulk capacitor voltage (VBLK) charges the VDD capacitor. During charging of the VDD capacitor the device bias supply current is less than 1.5 µA. When VDD reaches the 21-V UVLO turn-on threshold, the controller is enabled and the converter starts switching. The initial three cycles are limited to IPP(min). This allows sensing any initial input or output faults with minimal power delivery. After the initial three cycles at minimum IPP(min), the controller responds to the condition dictated by the control law. The converter remains in discontinuous mode during charging of the output capacitor(s), maintaining a constant output current until the output voltage is in regulation.