SLUS829G August   2008  – February 2020 UCC2897A

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Application Diagram
  4. Revision History
  5. Device Options
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Detailed Pin Descriptions
        1. 8.3.1.1  RDEL
        2. 8.3.1.2  RON
        3. 8.3.1.3  ROFF
        4. 8.3.1.4  VREF
        5. 8.3.1.5  SYNC
        6. 8.3.1.6  GND
        7. 8.3.1.7  CS
        8. 8.3.1.8  RSLOPE
        9. 8.3.1.9  FB
        10. 8.3.1.10 SS/SD
        11. 8.3.1.11 PGND
        12. 8.3.1.12 AUX
        13. 8.3.1.13 OUT
        14. 8.3.1.14 VDD
        15. 8.3.1.15 LINEUV
        16. 8.3.1.16 VIN
        17. 8.3.1.17 LINEOV
      2. 8.3.2 JFET Control and UVLO
      3. 8.3.3 Line Undervoltage Protection
      4. 8.3.4 Line Overvoltage Protection
      5. 8.3.5 Pulse Skipping
      6. 8.3.6 Synchronization
      7. 8.3.7 Gate Drive Connection
      8. 8.3.8 Bootstrap Biasing
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Oscillator
        2. 9.2.2.2 Soft Start
        3. 9.2.2.3 VDD Bypass Requirements
        4. 9.2.2.4 Delay Programming
        5. 9.2.2.5 Input Voltage Monitoring
        6. 9.2.2.6 Current Sense and Slope Compensation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Synchronization

The UCC2897A has a bi-directional synchronization pin. In the stand-alone operation the SYNC pin is driven by the internal oscillator of the UCC2897A which provides an approximately 5-V amplitude square-wave output. This signal synchronizes other PWM controllers or circuits requiring a constant frequency time-base. The synchronization output of the UCC2897A is generated when the internal-timing capacitor reaches the peak value. Therefore, the synchronization waveform does not coincide with the turnon of the main gate-driver output as it is usually implemented in PWM controllers.

The operation of the oscillator and other relevant waveforms in free-running and synchronized mode are shown in Figure 23.

UCC2897A a-sync_waveform_slus829.gifFigure 23. A Synchronization Waveform for SYNC Input, P-Channel

The most critical and unique feature of the oscillator is to limit the maximum-operating duty-cycle of the converter, which is achieved by accurately controlling the charge and discharge intervals of the on-board timing capacitor. The maximum on-time of the OUT pin, which is also the maximum duty-cycle of the active-clamp converter, is limited by the charging-interval of the timing capacitor. While the capacitor is reset to the initial voltage level, OUT is ensured to be off.

When synchronization is used, the rising edge of the signal terminates the charging period and initiates the discharge of the timing capacitor. Once the timing-capacitor voltage reaches the predefined valley-voltage, a new charge period starts automatically. This method of synchronization leaves the charge and discharge slopes of the timing-waveform unaffected thus maintains the maximum duty-cycle of the converter, independent of the operation mode.

Although the synchronization circuit is level sensitive, the actual synchronization event occurs at the rising-edge of the waveform, allowing the synchronizing pulse-width to vary significantly while certain limitations are observed. The minimum pulse-width should be sufficient to ensure reliable triggering of the internal-oscillator circuitry, therefore it is greater than approximately 50 nanoseconds. The other limiting factor is to keep it shorter than Equation 10.

Equation 10. (1 – DMAX) × TSYNC

where

  • TSYNC is the period of the synchronization frequency

When a pulse wider than that of Equation 10 is connected to the SYNC input, the oscillator is unable to maintain the maximum duty-cycle, originally set by the timing-resistor ratio (RON, ROFF). Furthermore, the timing-capacitor waveform has a flat portion as highlighted by the vertical marker in the timing diagram. During this flat portion of the waveform, both outputs are off, but this state is not compatible with the operation of active-clamp power converters. Therefore, this operating mode is not recommended.

Note that both outputs of the UCC2897A controller are off if the synchronization signal stays continuously high.

When both UCC2897A outputs are synchronized by tying their SYNC pins together, they operate in-phase. It is possible to set different maximum duty-cycle limits for both UCC2897A outputs and still synchronize them by a simple connection between their respective SYNC terminals.