SLUSEV2C June   2022  – March 2023 UCC28C50-Q1 , UCC28C51-Q1 , UCC28C52-Q1 , UCC28C53-Q1 , UCC28C54-Q1 , UCC28C55-Q1 , UCC28C56H-Q1 , UCC28C56L-Q1 , UCC28C57H-Q1 , UCC28C57L-Q1 , UCC28C58-Q1 , UCC28C59-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Description
        1. 8.3.1.1 COMP
        2. 8.3.1.2 FB
        3. 8.3.1.3 CS
        4. 8.3.1.4 RT/CT
        5. 8.3.1.5 GND
        6. 8.3.1.6 OUT
        7. 8.3.1.7 VDD
        8. 8.3.1.8 VREF
      2. 8.3.2  Undervoltage Lockout
      3. 8.3.3  ±1% Internal Reference Voltage
      4. 8.3.4  Current Sense and Overcurrent Limit
      5. 8.3.5  Reduced-Discharge Current Variation
      6. 8.3.6  Oscillator Synchronization
      7. 8.3.7  Soft Start
      8. 8.3.8  Enable and Disable
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Voltage Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Primary-to-Secondary Turns Ratio of the Flyback Transformer (NPS)
        2. 9.2.2.2  Primary Magnetizing Inductance of the Flyback Transformer (LM)
        3. 9.2.2.3  Number of Turns of the Flyback Transformer Windings
        4. 9.2.2.4  Current Sense Resistors (R24, R25) and Current Limiting
        5. 9.2.2.5  Primary Clamp Circuit (D7, D1, D3, R2, R28) to Limit Voltage Stress
        6. 9.2.2.6  Primary-Side Current Stress and Input Capacitor Selection
        7. 9.2.2.7  Secondary-Side Current Stress and Output Capacitor Selection
        8. 9.2.2.8  VDD Capacitors (C12, C18)
        9. 9.2.2.9  Gate Drive Network (R14, R16, Q6)
        10. 9.2.2.10 VREF Capacitor (C18)
        11. 9.2.2.11 RT/CT Components (R12, C15)
        12. 9.2.2.12 HV Start-Up Circuitry for VDD (Q1, Q2, D2, D4, D6, D8, R5)
        13. 9.2.2.13 Desensitization to CS-pin Noise by RC Filtering, Leading-Edge Blanking, and Slope Compensation
        14. 9.2.2.14 Voltage Feedback Compensation
          1. 9.2.2.14.1 Power Stage Gain, Poles, and Zeroes
          2. 9.2.2.14.2 Compensation Components
          3. 9.2.2.14.3 Bode Plots and Stability Margins
          4. 9.2.2.14.4 Stability Measurements
      3. 9.2.3 Application Curves
    3. 9.3 PCB Layout Recommendations
      1. 9.3.1 PCB Layout Routing Examples
    4. 9.4 Power Supply Recommendations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Related Links
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.8 VDD Capacitors (C12, C18)

During high-voltage (HV) startup from VIN, capacitor C12 must hold the VDD voltage above the UVLO turn-off threshold until the AUX voltage rises high enough to forward bias D12. If the value of C12 is not high enough the VDD voltage will decay below the UVLO turn-off threshold and the converter will prematurely stop switching. The controller will continuously cycle on-and-off as the VDD voltage transitions between UVLO turn-on and UVLO turn-off. One of the most common issues seen with new designs is the VDD capacitor value is too low and “there's no output voltage” or "it's not starting" is reported.

First, estimate a total HV soft start time, tSS. This estimate must include: (1) time for the COMP voltage to rise from 0 V to the PWM switching threshold (COMP to CS offset, 1.15 VTYP), and (2) time for the AUX voltage (on C13) to rise from 0 V until it forward biases D12. Typical values are 1-2 ms for the COMP rise time and 10-14 ms for the AUX rise time. Calculate the VDD capacitor value with the following equation

Equation 27. C V D D > ( I V D D _ M A X + 1.25 × f S W × Q G A T E ) × t S S ( V D D O N - V D D O F F )

Using IVDD_MAX = 2 mA, fSW = 42.5 kHz, QGATE = 11 nC, tSS = 14 ms (2ms + 12ms),

VDDON = 17.6 V, and VDDOFF = 14.5 V results in

Equation 28. C V D D > 11.7   µ F

Allowing ±20% initial capacitor tolerance and another 20% for endurance (life, temperature, etc.) means the VDD bulk capacitor must be at least 19.5 µF. Select the next higher standard capacitor value, 22 µF. This capacitor should be rated to at least the ABS MAX voltage of the VDD pin, 30 V.

The electrolytic bulk capacitor (C12) should be located relatively close to the VDD pin. On the other hand, the high-frequency bypass capacitor, C18, must be a ceramic type and be physically placed and grounded as close as possible to the VDD pin. A 1.0 μF, X7R capacitor is recommended for the high-frequency decoupling. To offset the effects of DC-bias, this capacitor must be rated to about 2x the expected VDD voltage (≥35V)