SLLSER8I June   2017  – March 2024 UCC5310 , UCC5320 , UCC5350 , UCC5390

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Function
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications for D Package
    7. 6.7  Insulation Specifications for DWV Package
    8. 6.8  Safety-Related Certifications For D Package
    9. 6.9  Safety-Related Certifications For DWV Package
    10. 6.10 Safety Limiting Values
    11. 6.11 Electrical Characteristics
    12. 6.12 Switching Characteristics
    13. 6.13 Insulation Characteristics Curves
    14. 6.14 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay, Inverting, and Noninverting Configuration
      1. 7.1.1 CMTI Testing
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supply
      2. 8.3.2 Input Stage
      3. 8.3.3 Output Stage
      4. 8.3.4 Protection Features
        1. 8.3.4.1 Undervoltage Lockout (UVLO)
        2. 8.3.4.2 Active Pulldown
        3. 8.3.4.3 Short-Circuit Clamping
        4. 8.3.4.4 Active Miller Clamp (UCC53x0M)
    4. 8.4 Device Functional Modes
      1. 8.4.1 ESD Structure
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing IN+ and IN– Input Filter
        2. 9.2.2.2 Gate-Driver Output Resistor
        3. 9.2.2.3 Estimate Gate-Driver Power Loss
        4. 9.2.2.4 Estimating Junction Temperature
      3. 9.2.3 Selecting VCC1 and VCC2 Capacitors
        1. 9.2.3.1 Selecting a VCC1 Capacitor
        2. 9.2.3.2 Selecting a VCC2 Capacitor
        3. 9.2.3.3 Application Circuits with Output Stage Negative Bias
      4. 9.2.4 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 PCB Material
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Certifications
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.11 Electrical Characteristics

VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, CL = 100-pF, TA = –40°C to +125°C, (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SUPPLY CURRENTS
IVCC1Input supply quiescent current1.672.4mA
IVCC2Output supply quiescent current1.11.8mA
SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VIT+(UVLO1)VCC1 Positive-going UVLO threshold voltage2.62.8V
VIT– (UVLO1)VCC1 Negative-going UVLO threshold voltage2.42.5V
Vhys(UVLO1)VCC1 UVLO threshold hysteresis0.1V
UCC5310MC, UCC5320SC,UCC5320EC,UCC5390SC,UCC5390EC, and UCC5350MC UVLO THRESHOLDS (12-V UVLO Version)
VIT+(UVLO2)VCC2 Positive-going UVLO threshold voltage1213V
VIT–(UVLO2)VCC2 Negative-going UVLO threshold voltage10.311V
Vhys(UVLO2)VCC2 UVLO threshold voltage hysteresis1V
UCC5350SB UVLO THRESHOLD (8-V UVLO Version)
VIT+(UVLO2) VCC2 Positive-going UVLO threshold voltage 8.7 9.4 V
VIT–(UVLO2) VCC2 Negative-going UVLO threshold voltage 7.3 8.0 V
Vhys(UVLO2) VCC2 UVLO threshold voltage hysteresis 0.7 V
LOGIC I/O
VIT+(IN)Positive-going input threshold voltage (IN+, IN–)0.55 × VCC10.7 × VCC1V
VIT–(IN)Negative-going input threshold voltage (IN+, IN–)0.3 × VCC10.45 × VCC1V
Vhys(IN)Input hysteresis voltage (IN+, IN–)0.1 × VCC1V
IIHHigh-level input leakage at IN+IN+ = VCC140240µA
IILLow-level input leakage at IN–IN– = GND1–240–40µA
IN– = GND1 – 5 V–310–80
GATE DRIVER STAGE
VOHHigh-level output voltage (VCC2 - OUT) and
(VCC2 - OUTH)		IOUT = –20 mA100240mV
VOLLow level output voltage (OUT and OUTL)UCC5320SC and UCC5320EC,
IN+ = low, IN– = high; IO = 20 mA		9.413mV
UCC5310MC,
IN+ = low, IN– = high; IO = 20 mA		1726
UCC5390SC and UCC5390EC,
IN+ = low, IN– = high; IO = 20 mA		23
UCC5350MC and UCC5350SB,
IN+ = low, IN– = high; IO = 20 mA		57
IOHPeak source currentUCC5320SC and UCC5320EC,
IN+ = high, IN– = low		2.44.3A
UCC5310MC, IN+ = high, IN– = low2.44.3
UCC5390SC and UCC5390EC,
IN+ = high, IN– = low		1017
UCC5350MC,
IN+ = high, IN– = low		510
UCC5350SB
IN+ = high, IN– = low		58.5
IOLPeak sink currentUCC5320SC and UCC5320EC,
IN+ = low, IN– = high		2.24.4A
UCC5310MC, IN+ = low, IN– = high1.12.2
UCC5390SC and UCC5390EC,
IN+ = low, IN– = high		1017
UCC5350MC,
IN+ = low, IN– = high		510
UCC5350SB
IN+ = low, IN– = high		510
ACTIVE MILLER CLAMP (UCC53xxM only)
VCLAMPLow-level clamp voltageUCC5310MC, ICLAMP = 20 mA2650mV
UCC5350MC, ICLAMP = 20 mA710
ICLAMPClamp low-level currentUCC5310MC, VCLAMP = VEE2 + 15 V1.12.2A
UCC5350MC, VCLAMP = VEE2 + 15 V510
ICLAMP(L)Clamp low-level current for low output voltageUCC5310MC, VCLAMP = VEE2 + 2 V0.71.5A
UCC5350MC, VCLAMP = VEE2 + 2 V510
VCLAMP-THClamp threshold voltageUCC5310MC and UCC5350MC2.12.3V
SHORT CIRCUIT CLAMPING
VCLP-OUTClamping voltage
(VOUTH – VCC2 or VOUT –VCC2)		IN+ = high, IN– = low, tCLAMP = 10 µs,
IOUTH or IOUT= 500 mA		11.3V
VCLP-OUTClamping voltage
(VEE2 – VOUTL or VEE2 – VCLAMP or VEE2 – VOUT)		IN+ = low, IN– = high, tCLAMP = 10 µs,
ICLAMP or IOUTL = –500 mA		1.5V
IN+ = low, IN– = high,
ICLAMP or IOUTL = –20 mA		0.91
ACTIVE PULLDOWN
VOUTSDActive pulldown voltage on OUTL, CLAMP, OUTIOUTL or IOUT = 0.1 × IOUTL(typ), VCC2 = open1.82.5V