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UCC5390

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10-A/10-A, 3-k/5-kVRMS single-channel isolated gate driver with 12-V UVLO, bipolar supply

Data sheet
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10-A/10-A, 3-k/5-kVRMS single-channel isolated gate driver with 12-V UVLO, bipolar supply

UCC5390

ACTIVE
Data sheet Order now

Product details

Parameters

Number of channels (#) 1 Isolation rating (Vrms) 3000, 5000 Power switch IGBT Peak output current (A) 17 DIN V VDE V 0884-10 transient overvoltage rating (Vpk) 4242, 7000 DIN V VDE V 0884-10 working voltage (Vpk) 990, 2121 Output VCC/VDD (Max) (V) 33 Output VCC/VDD (Min) (V) 13.2 Input VCC (Min) (V) 3 Input VCC (Max) (V) 15 Prop delay (ns) 65 Operating temperature range (C) -40 to 125 Undervoltage lockout (Typ) 12 open-in-new Find other Isolated gate drivers

Package | Pins | Size

SOIC (D) 8 19 mm² 4.9 x 3.9 SOIC (DWV) 8 67 mm² 5.85 x 11.5 open-in-new Find other Isolated gate drivers

Features

  • Feature Options
    • Split Outputs (UCC53x0S)
    • UVLO Referenced to GND2 (UCC53x0E)
    • Miller Clamp Option (UCC53x0M)
  • 8-pin D (4-mm Creepage) and
    DWV (8.5mm Creepage) Package
  • 60-ns (Typical) Propagation Delay
  • 100-kV/µs Minimum CMTI
  • Isolation Barrier Life > 40 Years
  • 3-V to 15-V Input Supply Voltage
  • Up to 33-V Driver Supply Voltage
    • 8-V and 12-V UVLO Options
  • Negative 5-V Handling Capability on Input Pins
  • Safety-Related Certifications:
    • 7000-VPK Isolation DWV (Planned) and 4242-VPK Isolation D per DIN V VDE V 0884-11:2017-01 and DIN EN 61010-1
    • 5000-VRMS DWV and 3000-VRMS D
      Isolation Rating for 1 minute per UL 1577
    • CQC Certification per GB4943.1-2011
      D and DWV (Planned)
  • CMOS Inputs
  • Operating Temperature: –40°C to +125°C

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Description

The UCC53x0 is a family of single-channel, isolated gate drivers designed to drive MOSFETs, IGBTs, SiC MOSFETs, and GaN FETs (UCC5350SBD). The UCC53x0S provides a split output that controls the rise and fall times individually. The UCC53x0M connects the gate of the transistor to an internal clamp to prevent false turnon caused by Miller current. The UCC53x0E has its UVLO2 referenced to GND2 to get a true UVLO reading.

The UCC53x0 is available in a 4 mm SOIC-8 (D) or 8.5 mm SOIC-8 (DWV) package and can support isolation voltage up to 3 kVRMS and 5 kVRMS respectively. With these various options the UCC53x0 family is a good fit for motor drives and industrial power supplies.

Compared to an optocoupler, the UCC53x0 family has lower part-to-part skew, lower propagation delay, higher operating temperature, and higher CMTI.

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Technical documentation

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Type Title Date
* Datasheet UCC53x0 Single-Channel Isolated Gate Drivers datasheet (Rev. F) Dec. 06, 2018
Technical article The impact of an isolated gate driver’s input stage for motor-drive applications Sep. 29, 2020
E-book Ein Techniker-Leitfaden für Industrieroboter-Designs Mar. 25, 2020
Application note External Gate Resistor Selection Guide (Rev. A) Feb. 28, 2020
Application note Understanding Peak IOH and IOL Currents (Rev. A) Feb. 28, 2020
E-book E-book: An engineer’s guide to industrial robot designs Feb. 12, 2020
More literature VDE certificate for basic isolation for DIN VDE V 0884-11:2017-01 (Rev. Q) Sep. 20, 2019
More literature CQC Product Certificate 3 Jul. 22, 2019
More literature UL Certification E181974 Vol 4. Sec 7 (Rev. B) Jul. 22, 2019
Technical article How to achieve higher system robustness in DC drives, part 3: minimum input pulse Sep. 19, 2018
Application note Enable Function with Unused Differential Input Jul. 11, 2018
Technical article How to achieve higher system robustness in DC drives, part 2: interlock and deadtime May 30, 2018
Technical article Boosting efficiency for your solar inverter designs May 24, 2018
White paper Isolation in solar power converters: Understanding the IEC62109-1 safety standar (Rev. A) May 18, 2018
White paper Understanding failure modes in isolators (Rev. A) May 10, 2018
User guide UCC5390SCD With Isolated Bias Supply (Rev. A) Feb. 07, 2018
User guide UCC5390ECDWV Isolated Gate Driver Evaluation Module User's Guide Jan. 25, 2018
User guide UCC53x0xD Evaluation Module Jun. 21, 2017
Application note Common-mode transient immunity for isolated gate drivers Oct. 30, 2015
White paper High-voltage reinforced isolation: Definitions and test methodologies Oct. 16, 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
49
Description
UCC5320SCEVM is an Evaluation Module used to evaluate UCC53xx family of devices and it provides user with flexiblity of configuring  driver to Split output, miller clamp or UVLO based on the device used . The EVM features enough test points & jumper options for one to evaluate the device (...)
Features
  • 100-kV/us Minimum and 120-kV/us Typical Common-Mode Transient (CMTI) at VCM = 1000V
  • 1A, 2A, 5A, 10A Peak Source/Sink Drive current options
  • Flexibility of all three coniguratinos of family: Split Outputs, UVLO and Miller Clamp
  • Isolation Surge Withstand Voltage 10000-Vpk
  • 80-ns (max) Prop Delay
View details
EVALUATION BOARD Download
document-generic User guide
49
Description
UCC5390ECDWVEVM is designed for evaluating the UCC53xxDWV family, which is a 5.0-kVRMS Isolated Single-Channel Gate Driver with 10-A source and 10-A sink peak current capability. This EVM could be served to evaluate the driver IC against its datsheet. The EVM can also be used as Driver IC component (...)
Features
  • High performance driver with input and output interface
  • Ability to test most data sheet parameters
  • Ability to compare performance of various drivers with compatible pinout
View details
EVALUATION BOARD Download
document-generic User guide
49
Description
The UCC5390SCDEVM-010 is a complete single channel isolated gate drive board including reconfigurable bias supply providing wide range of drive voltages. The EVM is based on a 17-A split output basic insulation UCC5390SCD Driver in SOIC-8 package. The design also includes SN6505B based bias supply (...)
Features
  • EVM used as reference design for isolated bias supply
  • High performance driver with input and output interface
  • Ability to test most data sheet parameters
  • Ability to compare performance of various drivers with compatible pinout
View details

Design tools & simulation

SIMULATION MODEL Download
SLLM366.ZIP (53 KB) - PSpice Model
SIMULATION MODEL Download
SLLM369.ZIP (3 KB) - PSpice Model
SIMULATION MODEL Download
SLLM370.ZIP (52 KB) - PSpice Model
SIMULATION MODEL Download
SLLM371.ZIP (3 KB) - PSpice Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
View details
CALCULATION TOOL Download
SLURAY7.ZIP (1677 KB)

Reference designs

REFERENCE DESIGNS Download
Reinforced Isolated Phase Current Sense Reference Design with Small Delta Sigma Modulators
TIDA-00914 — This reference design realizes a reinforced isolated 3-phase inverter sub-system using isolated IGBT gate drivers and isolated current/voltage sensors. Precise in-line shunt based motor phase current sensing is done with AMC1306E25 delta sigma modulators. The modulator output is Manchester-encoded (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Basic Isolated Three-Phase Compact Power Stage Reference Design for Industrial Drives
TIDA-01420 — This three-phase, compact power stage reference design for industrial drives, which uses a UCC53xx gate driver to support basic capacitive isolation requirements, provides an increased lifespan and better propagation delay match over optocouplers to minimize inverter deadband distortions and losses (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
SOIC (D) 8 View options
SOIC (DWV) 8 View options

Ordering & quality

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  • Ongoing reliability monitoring

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