10-A/10-A, 3-k/5-kVRMS single-channel isolated gate driver with 12-V UVLO, bipolar supply
Product details
Parameters
Package | Pins | Size
Features
- Feature Options
- Split Outputs (UCC53x0S)
- UVLO Referenced to GND2 (UCC53x0E)
- Miller Clamp Option (UCC53x0M)
- 8-pin D (4-mm Creepage) and
DWV (8.5mm Creepage) Package - 60-ns (Typical) Propagation Delay
- 100-kV/µs Minimum CMTI
- Isolation Barrier Life > 40 Years
- 3-V to 15-V Input Supply Voltage
- Up to 33-V Driver Supply Voltage
- 8-V and 12-V UVLO Options
- Negative 5-V Handling Capability on Input Pins
- Safety-Related Certifications:
- 7000-VPK Isolation DWV (Planned) and 4242-VPK Isolation D per DIN V VDE V 0884-11:2017-01 and DIN EN 61010-1
- 5000-VRMS DWV and 3000-VRMS D
Isolation Rating for 1 minute per UL 1577 - CQC Certification per GB4943.1-2011
D and DWV (Planned)
- CMOS Inputs
- Operating Temperature: –40°C to +125°C
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Description
The UCC53x0 is a family of single-channel, isolated gate drivers designed to drive MOSFETs, IGBTs, SiC MOSFETs, and GaN FETs (UCC5350SBD). The UCC53x0S provides a split output that controls the rise and fall times individually. The UCC53x0M connects the gate of the transistor to an internal clamp to prevent false turnon caused by Miller current. The UCC53x0E has its UVLO2 referenced to GND2 to get a true UVLO reading.
The UCC53x0 is available in a 4 mm SOIC-8 (D) or 8.5 mm SOIC-8 (DWV) package and can support isolation voltage up to 3 kVRMS and 5 kVRMS respectively. With these various options the UCC53x0 family is a good fit for motor drives and industrial power supplies.
Compared to an optocoupler, the UCC53x0 family has lower part-to-part skew, lower propagation delay, higher operating temperature, and higher CMTI.
Technical documentation
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- 100-kV/us Minimum and 120-kV/us Typical Common-Mode Transient (CMTI) at VCM = 1000V
- 1A, 2A, 5A, 10A Peak Source/Sink Drive current options
- Flexibility of all three coniguratinos of family: Split Outputs, UVLO and Miller Clamp
- Isolation Surge Withstand Voltage 10000-Vpk
- 80-ns (max) Prop Delay
Description
Features
- High performance driver with input and output interface
- Ability to test most data sheet parameters
- Ability to compare performance of various drivers with compatible pinout
Description
Features
- EVM used as reference design for isolated bias supply
- High performance driver with input and output interface
- Ability to test most data sheet parameters
- Ability to compare performance of various drivers with compatible pinout
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
Reference designs
Design files
-
download TIDA-00914 Assembly Drawing.pdf (539KB) -
download TIDA-00914 PCB.pdf (1968KB) -
download TIDA-00914 Gerber.zip (460KB) -
download TIDA-00914 BOM (Rev. A).pdf (40KB) -
download TIDA-00914 CAD Files (Rev. A).zip (1704KB)
Design files
-
download TIDA-01420 BOM.pdf (102KB) -
download TIDA-01420 Assembly Drawing.pdf (594KB) -
download TIDA-01420 PCB.pdf (2861KB) -
download TIDA-01420 CAD Files.zip (1903KB) -
download TIDA-01420 Gerber.zip (332KB)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
SOIC (D) | 8 | View options |
SOIC (DWV) | 8 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Support & training
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