SLUSE29E May   2020  – February 2024 UCC5350-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (continued)
  6. 5 Pin Configuration and Function
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications for D Package
    7. 6.7  Insulation Specifications for DWV Package
    8. 6.8  Safety-Related Certifications For D Package
    9. 6.9  Safety-Related Certifications For DWV Package
    10. 6.10 Safety Limiting Values
    11. 6.11 Electrical Characteristics
    12. 6.12 Switching Characteristics
    13. 6.13 Insulation Characteristics Curves
    14. 6.14 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay, Inverting, and Noninverting Configuration
      1. 7.1.1 CMTI Testing
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supply
      2. 8.3.2 Input Stage
      3. 8.3.3 Output Stage
      4. 8.3.4 Protection Features
        1. 8.3.4.1 Undervoltage Lockout (UVLO)
        2. 8.3.4.2 Active Pulldown
        3. 8.3.4.3 Short-Circuit Clamping
        4. 8.3.4.4 Active Miller Clamp
    4. 8.4 Device Functional Modes
      1. 8.4.1 ESD Structure
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing IN+ and IN– Input Filter
        2. 9.2.2.2 Gate-Driver Output Resistor
        3. 9.2.2.3 Estimate Gate-Driver Power Loss
        4. 9.2.2.4 Estimating Junction Temperature
      3. 9.2.3 Selecting VCC1 and VCC2 Capacitors
        1. 9.2.3.1 Selecting a VCC1 Capacitor
        2. 9.2.3.2 Selecting a VCC2 Capacitor
        3. 9.2.3.3 Application Circuits with Output Stage Negative Bias
      4. 9.2.4 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 PCB Material
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Certifications
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.2 Gate-Driver Output Resistor

The external gate-driver resistors, RG(ON) and RG(OFF) are used to:

  1. Limit ringing caused by parasitic inductances and capacitances
  2. Limit ringing caused by high voltage or high current switching dv/dt, di/dt, and body-diode reverse recovery
  3. Fine-tune gate drive strength, specifically peak sink and source current to optimize the switching loss
  4. Reduce electromagnetic interference (EMI)

The output stage has a pull-up structure consisting of a P-channel MOSFET and an N-channel MOSFET in parallel. The combined typical peak source current is 10 A for UCC5350-Q1. Use Equation 1 to estimate the peak source current.

Equation 1. I O H = V C C 2 - V E E 2 R N M O S | | R O H + R G O N + R G F E T _ I n t

where

  • RON is the external turn-on resistance, which is 2.2 Ω in this example.
  • RGFET_Int is the power transistor internal gate resistance, found in the power transistor data sheet. We will assume 1.8Ω for our example.
  • IOH is the typical peak source current which is the minimum value between 10 A, the gate-driver peak source current, and the calculated value based on the gate-drive loop resistance.

In this example, the peak source current is approximately 3.36 A as calculated in Equation 2.

Equation 2. I O H = V C C 2 - V E E 2 R N M O S | | R O H + R G O N + R G F E T _ I n t = 18   V 1.54 Ω | | 12 Ω + 2.2 Ω + 1.8 Ω ≈ 3.36 A

Similarly, use Equation 3 to calculate the peak sink current.

Equation 3. I O L = V C C 2 - V E E 2 R O L + R G O F F + R G F E T _ I n t

where

  • ROFF is the external turn-off resistance, which is 2.2 Ω in this example.
  • IOL is the typical peak sink current which is the minimum value between 10 A, the gate-driver peak sink current, and the calculated value based on the gate-drive loop resistance.

In this example, the peak sink current is the minimum value between Equation 4 and 10 A.

Equation 4. I O L = V C C 2 - V E E 2 R O L + R G O F F + R G F E T _ I n t = 18   V 0.26 Ω + 2.2 Ω + 1.8 Ω ≈ 4.23 A
Note:

The estimated peak current is also influenced by PCB layout and load capacitance. Parasitic inductance in the gate-driver loop can slow down the peak gate-drive current and introduce overshoot and undershoot. Therefore, TI strongly recommends that the gate-driver loop should be minimized. Conversely, the peak source and sink current is dominated by loop parasitics when the load capacitance (CISS) of the power transistor is very small (typically less than 1 nF) because the rising and falling time is too small and close to the parasitic ringing period.