SLLSER8F June   2017  – January 2019 UCC5310 , UCC5320 , UCC5350 , UCC5390

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1. 3.1 Functional Block Diagram (S, E, and M Versions)
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Function
    1.     Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications for D Package
    7. 7.7  Insulation Specifications for DWV Package
    8. 7.8  Safety-Related Certifications For D Package
    9. 7.9  Safety-Related Certifications For DWV Package
    10. 7.10 Safety Limiting Values
    11. 7.11 Electrical Characteristics
    12. 7.12 Switching Characteristics
    13. 7.13 Insulation Characteristics Curves
    14. 7.14 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Propagation Delay, Inverting, and Noninverting Configuration
      1. 8.1.1 CMTI Testing
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power Supply
      2. 9.3.2 Input Stage
      3. 9.3.3 Output Stage
      4. 9.3.4 Protection Features
        1. 9.3.4.1 Undervoltage Lockout (UVLO)
        2. 9.3.4.2 Active Pulldown
        3. 9.3.4.3 Short-Circuit Clamping
        4. 9.3.4.4 Active Miller Clamp (UCC53x0M)
    4. 9.4 Device Functional Modes
      1. 9.4.1 ESD Structure
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Designing IN+ and IN– Input Filter
        2. 10.2.2.2 Gate-Driver Output Resistor
        3. 10.2.2.3 Estimate Gate-Driver Power Loss
        4. 10.2.2.4 Estimating Junction Temperature
      3. 10.2.3 Selecting VCC1 and VCC2 Capacitors
        1. 10.2.3.1 Selecting a VCC1 Capacitor
        2. 10.2.3.2 Selecting a VCC2 Capacitor
        3. 10.2.3.3 Application Circuits With Output Stage Negative Bias
      4. 10.2.4 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 PCB Material
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Certifications
    3. 13.3 Related Links
    4. 13.4 Receiving Notification of Documentation Updates
    5. 13.5 Community Resources
    6. 13.6 Trademarks
    7. 13.7 Electrostatic Discharge Caution
    8. 13.8 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Output Stage

The output stages of the UCC53x0 family feature a pullup structure that delivers the highest peak-source current when it is most needed which is during the Miller plateau region of the power-switch turnon transition (when the power-switch drain or collector voltage experiences dV/dt). The output stage pullup structure features a P-channel MOSFET and an additional pullup N-channel MOSFET in parallel. The function of the N-channel MOSFET is to provide a brief boost in the peak-sourcing current, which enables fast turn-on. Fast turn-on is accomplished by briefly turning on the N-channel MOSFET during a narrow instant when the output is changing states from low to high. Table 1 lists the typical internal resistance values of the pullup and pulldown structure.

Table 1. UCC53x0 On-Resistance

DEVICE OPTION RNMOS ROH ROL RCLAMP UNIT
UCC5320SC and UCC5320EC 4.5 12 0.65 Not applicable Ω
UCC5310MC 4.5 12 1.3 1.3 Ω
UCC5390SC and UCC5390EC 0.76 12 0.13 Not applicable Ω
UCC5350MC 1.54 12 0.26 0.26 Ω
UCC5350SB 1.54 12 0.26 Not applicable Ω

The ROH parameter is a DC measurement and is representative of the on-resistance of the P-channel device only. This parameter is only for the P-channel device, because the pullup N-channel device is held in the OFF state in DC condition and is turned on only for a brief instant when the output is changing states from low to high. Therefore, the effective resistance of the UCC53x0 pullup stage during this brief turnon phase is much lower than what is represented by the ROH parameter, which yields a faster turnon. The turnon-phase output resistance is the parallel combination ROH || RNMOS.

The pulldown structure in the UCC53x0 S and E versions is simply composed of an N-channel MOSFET. For the M version, an additional FET is connected in parallel with the pulldown structure when the CLAMP and OUT pins are connected to the gate of the IGBT or MOSFET. The output voltage swing between VCC2 and VEE2 provides rail-to-rail operation.

UCC5310 UCC5320 UCC5350 UCC5390 Output-Stage.gifFigure 52. Output Stage—S Version
UCC5310 UCC5320 UCC5350 UCC5390 Output-Stage-E.gifFigure 53. Output Stage—E Version
UCC5310 UCC5320 UCC5350 UCC5390 Output-Stage-M.gifFigure 54. Output Stage—M Version