SLUSF42 December   2022 UCC5871-Q1

PRODUCTION DATA  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Pin Configuration and Functions
  6. 6Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  SPI Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7Layout
    1. 7.1 Layout Guidelines
      1. 7.1.1 Component Placement
      2. 7.1.2 Grounding Considerations
      3. 7.1.3 High-Voltage Considerations
      4. 7.1.4 Thermal Considerations
    2. 7.2 Layout Example
  8. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC1 Supply voltage input side 3 5.5 V
VCC2 Positive supply voltage secondary side (VCC2 - GND2) 15 30 V
VEE2 Negative supply voltage output side (VEE2 - GND2) –12 0 V
VSUP2 Total supply voltage output side (VCC2 - VEE2) 15 30 V
VIH High-level IO voltage (ASC, ASC_EN, IN+, IN-, nCS, SCLK, SDI) 0.7*VCC1 VCC1 V
VIL Low-level IO voltage (ASC, ASC_EN, IN+, IN-, nCS, SCLK, SDI) 0 0.3*VCC1 V
IOHP Source current for primary side outputs (nFLT2, SDO) 5 mA
IOLP Sink current for primary side outputs (nFLTx, SDO) 5 mA
IOH Driver output source current from OUTH (1) 15 A
IOL Driver output sink current into OUTL (1) 15 A
VAI* Voltage on analog input (AI) pins referenced to GND2 0 VREF+0.1 V
VVREG1 Output voltage at VREG1 referenced to GND1 (2) 1.8 V
VVREG2 Output voltage at VREG2 referenced to VEE2(3) 1.8 V
VVBST Output voltage at VBST referenced to OUTH(4) Vcc2 + 4.5 V
VVREF Voltage on the VREF pin vs GND2(5) 0 4 4.1 V
CMTI Common mode transient immunity rating (dV/dt rate across the isolation barrier) 100 kV/us
fPWM PWM input frequency (IN+ and IN- pins) 50 kHz
fSPI SPI clock frequency 4 MHz
TJ Maximum junction temperature – 40 150 ℃
tPWM PWM input pulse width (IN+ and IN- pins) 250 ns
(1) External gate resistor needs to be used to limit the max drive current to be not more than 15A.
(2) Connect a decoupling capacitor of 0.1uF+4.7uF between VREG1 and GND1.  Do not connect external supply.
(3) Connect a decoupling capacitor of 0.1uF+4.7uF between VREG2 and VEE2. Do not connect external supply.
(4) Connect a decoupling capacitor of 100nF between VBST and OUTH.  Do not connect external supply.
(5) Connect a decoupling capacitor of 1.0uF on the VREF pin.