SLUSF42 December   2022 UCC5871-Q1

PRODUCTION DATA  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Pin Configuration and Functions
  6. 6Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  SPI Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7Layout
    1. 7.1 Layout Guidelines
      1. 7.1.1 Component Placement
      2. 7.1.2 Grounding Considerations
      3. 7.1.3 High-Voltage Considerations
      4. 7.1.4 Thermal Considerations
    2. 7.2 Layout Example
  8. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.10 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tr OUTH rise time CLOAD = 10 nF 150 ns
tf OUTL fall time CLOAD = 10 nF 150 ns
tPLH, tPHL Propagation delay from INP to OUTx CLOAD = 0.1 nF, tGLITCH_IO = 00b 150 ns
tsk(p) Pulse skew |tPHL - tPLH| CLOAD = 0.1 nF 20 50 ns
tsk-pp Part-to-part skew - same edge CLOAD = 0.1 nF 20 50 ns
fmax Maximum switching frequency CLOAD = 0.1 nF, ADC disabled 50 kHz
tdFLT1 Delay from fault detection to nFLT1 pin goes LOW. CLOAD = 100pF, REPU = 10kΩ 5 μs
tdFLT2 Delay from fault detection to nFLT2 pin goes LOW. CLOAD = 100pF, REPU = 10kΩ 25  μs
tASC_EN Required hold time for ASC after ASC_EN transition  1
μs
tASC_DLY Delay from the ASC edge to OUTx transition (primary side) ASC rising 2  μs
tASC_DLY ASC falling 0.1 μs
Delay from the AI6 (ASC) edge to OUTx transition (secondary side) AI6 rising 1.8 μs
AI6 falling 0.3 μs
tMUTE PWM input mute time in case of DESAT, SC, and PS_TSD fault PWM_MUTE_EN = 1 10 ms
tGLITCH_IO Deglitch time for the primary side IO pins (exclude nCS, CLK, SDI, and SDO pins)  IO_DEGLITCH = 00b 0 ns
IO_DEGLITCH = 01b 70 ns
IO_DEGLITCH = 10b 140 ns
IO_DEGLITCH = 11b 210 ns
tDEAD Dead time for shoot through protection TDEAD = 000000b 0 ns
TDEAD = 000001b 93  105 154  ns
TDEAD = 000010b 159   175 228  ns
TDEAD = 000011b 225   245 302  ns
TDEAD = 000100b 291  315 376  ns
TDEAD = 111111b 4178.3 4445 4748.8 ns
tSTARTUP System start-up time (from power ready to nFLTx pins go high) 5 ms
tVREGxOV VREG1 and VREG2 overvoltage detection deglitch time 30 μs