SLUSC66E March   2015  – February 2017 UCD3138A


  1. Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. Device Comparison
    1. 2.1 Product Selection Matrix
  3. Pin Configuration and Functions
    1. 3.1 UCD3138A RGC Package
    2. 3.2 UCD3138A RMH Package
    3. 3.3 UCD3138A RJA Package
  4. Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 PMBus/SMBus/I2C Timing
    7. 4.7 Peripherals
      1. 4.7.1 Digital Power Peripherals (DPPs)
        1. Front End
        2. DPWM Module
        3. DPWM Events
        4. High Resolution DPWM
        5. Oversampling
        6. DPWM Interrupt Generation
        7. DPWM Interrupt Scaling/Range
        8. DPWM Synchronization
        9. Synchronous Rectifier Dead-Time Optimization Peripheral
    8. 4.8 Typical Temperature Characteristics
  5. Parametric Measurements Information
    1. 5.1 Power-On Reset (POR) and Brown-Out Reset (BOR)
  6. Detailed Description
    1. 6.1 Overview
    2. 6.2 ARM Processor
    3. 6.3 Memory
      1. 6.3.1 CPU Memory Map and interruptions
      2. 6.3.2 Boot ROM
      3. 6.3.3 Customer Boot Program
      4. 6.3.4 Flash Management
    4. 6.4 System Module
      1. 6.4.1 Address Decoder (DEC)
      2. 6.4.2 Memory Management Controller (MMC)
      3. 6.4.3 System Management (SYS)
      4. 6.4.4 Central Interrupt Module (CIM)
    5. 6.5 Feature Description
      1. 6.5.1  Sync FET Ramp and IDE Calculation
      2. 6.5.2  Automatic Mode Switching
        1. Phase Shifted Full Bridge Example
        2. LLC Example
        3. Mechanism for Automatic Mode Switching
      3. 6.5.3  DPWMC, Edge Generation, IntraMux
      4. 6.5.4  Filter
        1. Loop Multiplexer
        2. Fault Multiplexer
      5. 6.5.5  Communication Ports
        1. SCI (UART) Serial Communication Interface
        2. PMBus Interfacte
        3. General Purpose ADC12
        4. Timers
          1. 24-bit PWM Timer
          2. 16-Bit PWM Timers
          3. Watchdog Timer
      6. 6.5.6  Miscellaneous Analog
      7. 6.5.7  Package ID Information
      8. 6.5.8  Brownout
      9. 6.5.9  Global I/O
      10. 6.5.10 Temperature Sensor Control
      11. 6.5.11 I/O Mux Control
      12. 6.5.12 Current Sharing Control
      13. 6.5.13 Temperature Reference
  7. Device Functional Modes
    1. 7.1 Normal Mode
    2. 7.2 DPWM Multiple Output Mode
    3. 7.3 DPWM Resonant Mode
    4. 7.4 Triangular Mode
    5. 7.5 Leading Edge Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. PCMC (Peak Current Mode Control) PSFB (Phase-Shifted Full Bridge) Hardware Configuration Overview
        2. DPWM Initialization for PSFB
      3. 8.2.3 Fixed Signals to Bridge
      4. 8.2.4 Dynamic Signals to Bridge
      5. 8.2.5 System Initialization for PCM
        1. Use of Front Ends and Filters in PSFB
        2. Peak Current Detection
        3. Peak Current Mode (PCM)
      6. 8.2.6 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Power Supply Decoupling and Bulk Capacitors
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. Tools and Documentation
    2. 11.2 Documentation Support
      1. 11.2.1 References
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical Packaging and Orderable Information
    1. 12.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Device Overview


  • Digital Control of up to 3 Independent Feedback Loops
    • Dedicated PID-Based Hardware
    • 2-Pole, 2-Zero Configurable
    • Nonlinear Control
  • Soft-Start and Soft-Stop with and without Prebias
  • Fast Input Voltage Feed Forward Hardware
  • Synchronous Rectifier Dead Time Optimization Peripheral to Use with UCD7138 Synchronous Rectifier Driver
  • Up to 16 MHz Error Analog-to-Digital Converter (EADC)
    • Configurable Resolution as Small as 1 mV/LSB
    • Automatic Resolution Selection
    • Up to 8× Oversampling
    • Hardware-Based Averaging (up to 8×)
    • 10-Bit Effective DAC With 4 Bits of Dither
    • Adaptive Sample Trigger Positioning
  • Up to 8 High-Resolution Digital Pulse Width Modulated (DPWM) Outputs
    • 250-ps Pulse Width Resolution
    • 4-ns Frequency and Phase Resolution
    • Adjustable Phase-Shift Between Outputs
    • Adjustable Dead-band Between Pairs
    • Cycle-by-Cycle Duty Cycle Matching
    • Up to 2-MHz Switching Frequency
  • Configurable PWM Edge Movement
    • Trailing Modulation
    • Leading Modulation
    • Triangular Modulation
  • Configurable Feedback Control
    • Voltage Mode
    • Average Current Mode
    • Peak Current Mode Control
    • Constant Current
    • Constant Power
  • Configurable Modulation Methods
    • Frequency Modulation
    • Phase-Shift Modulation
    • Pulse Width Modulation
  • Fast, Automatic, and Smooth Mode Switching
    • Frequency Modulation and PWM
    • Phase-Shift Modulation and PWM
    • Frequency Modulation and Phase-Shift Modulation
  • High Efficiency and Light Load Management
    • Burst Mode
    • Ideal Diode Emulation
    • Synchronous Rectifier Soft On/Off
    • Low IC Standby Power
  • Primary Side Voltage Sensing
  • Copper Trace Current Sensing
  • Flux and Phase Current Balancing
  • Current Share Bus Support
    • Average or Master and Slave
  • Feature Rich Fault Protection Options
    • 7 High-Speed Analog Comparators
    • Cycle-by-Cycle Current Limiting
    • Programmable Fault
    • External Fault Capability
    • 10 Digital Comparators
    • Programmable Blanking Time
  • Synchronization of DPWM Waveforms Between Multiple UCD3138A devices
  • 14-Channel, 12-Bit, 267-ksps General-Purpose ADC
    • Programmable Averaging Filters
    • Dual Sample and Hold
  • Internal Temperature Sensor
  • Fully Programmable High-Performance 31.25-MHz, 32-Bit ARM7TDMI-S™ Processor
    • 32 KB of Program Flash
    • 2 KB of Data Flash with ECC
    • 4 KB of Data RAM
    • Firmware Boot-Load in the Field via PMBus or UART
  • Communication Peripherals
    • PMBus
    • 1 UART
  • UART Auto-baud Rate Adjustment
  • Timer Capture with Selectable Input Pins
  • Up to 5 Additional General Purpose Timers
  • Built In Watchdog: BOD and POR
  • 64-Pin QFN and 40-Pin QFN Package
  • Operating Temperature: –40°C to +125°C
  • Debug Interface
    • Code Composer Studio™ with JTAG Interface
    • Fusion Digital Power™ Designer GUI Support


  • Power Supplies and Telecom Rectifiers
  • Power Factor Correction
  • Isolated DC-DC Modules


The UCD3138A is a digital power supply controller from Texas Instruments offering superior levels of integration and performance in a single-chip solution. The flexible nature of the UCD3138A makes it suitable for a wide variety of power conversion applications. In addition, multiple peripherals inside the device have been specifically optimized to enhance the performance of AC-DC and isolated DC-DC applications and reduce the solution component count in the IT and network infrastructure space.

The UCD3138A controller is a fully programmable solution offering customers complete control of their application, along with ample ability to differentiate their solution. At the same time, TI is committed to simplifying our customers' development effort by offering best-in-class development tools, including application firmware, Code Composer Studio™ software development environment, and TI’s power development GUI which lets customers configure and monitor key system parameters.

At the core of the UCD3138A controller are the digital control loop peripherals, also known as Digital Power Peripherals (DPPs). Each DPP implements a high-speed digital control loop consisting of a dedicated error analog-to-digital converter (EADC), a PID-based 2-pole-2-zero digital compensator and DPWM outputs with 250-ps pulse width resolution. The device also contains a 12-bit, 267-ksps general-purpose ADC with up to 14 channels, timers, interrupt control, PMBus, and UART communications ports. The device is based on a 32-bit ARM7TDMI-S RISC microcontroller that performs real-time monitoring, configures peripherals, and manages communications. The ARM microcontroller executes its program out of programmable flash memory as well as on-chip RAM and ROM.

In addition to the DPP, specific power management peripherals have been added to enable high efficiency across the entire operating range, high integration for increased power density, reliability, and lowest overall system cost and high flexibility with support for the widest number of control schemes and topologies. Such peripherals include: light load burst mode, synchronous rectification, automatic mode switching, input voltage feed forward, copper trace current sense, ideal diode emulation, constant current constant power control, synchronous rectification soft on and off, peak current mode control, flux balancing, secondary side input voltage sensing, high-resolution current sharing, hardware-configurable soft-start operation with pre-bias, as well as several other features. The device optimizes topology support for voltage mode and peak current mode controlled phase-shifted full bridge, single and dual phase PFC, bridge-less PFC, hard-switched full bridge and half bridge, and LLC half bridge and full bridge.

The UCD3139A is a functional variant of the UCD3138A Digital Power Controller that includes significant improvements over the UCD3138 device For a description of the complete changes made in the UCD3138A, refer to UCD3138A Migration Guide.

Device Information(1)

UCD3138A RGC VQFN (64) 9.00 mm × 9.00 mm
RJA VQFN (40)(3) 6.00 mm × 6.00 mm
RMH WQFN (40) 6.00 mm × 6.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.
  2. 40-pin 6 x 6 x 0.75 mm ultra-thin QFN with corner anchors optimized for IPC9592A Temperature Cycle Testing.
  3. Recommended for new 40-pin designs, optimized for improved performance under temperature cycling test for board level reliability (BLR).

Functional Block Diagram

Figure 1-1 shows a functional block diagram of the device.

UCD3138A fbd_slusc66.gif Figure 1-1 Functional Block Diagram
UCD3138A front-page-simplified-application_slusc66.gif
Figure 1-2 Synchronous Rectifier Peripheral Use with Synchronous Rectifier Driver