SLVSCS1B March   2015  – May 2015 UCD7138

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Body-Diode Conduction Detection
      2. 8.3.2 Gate Turnon and Turnoff
      3. 8.3.3 VCC and Undervoltage Lockout
      4. 8.3.4 Operating Supply Current
      5. 8.3.5 Driver Stage
    4. 8.4 Device Functional Modes
      1. 8.4.1 UVLO Mode
      2. 8.4.2 Normal Operation Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Half-Bridge LLC
        1. 9.2.1.1 Design Requirements
          1. 9.2.1.1.1 Gate Input
          2. 9.2.1.1.2 Gate Output
          3. 9.2.1.1.3 Drain-to-Source Voltage Sensing
          4. 9.2.1.1.4 DTC Output
          5. 9.2.1.1.5 Turn-on Edge Optimization
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Design Without SR-Control Optimization
          2. 9.2.1.2.2 Setting the DTC Detection Window
          3. 9.2.1.2.3 Setting the Clamps
          4. 9.2.1.2.4 Setting the DTC Optimization Target and Hysteresis
          5. 9.2.1.2.5 Setting the DTC Negative Current Fault Protection
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resource
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

Proper PCB layout is extremely important in a high-current, fast-switching circuit to provide appropriate device operation and design robustness. The following circuit layout guidelines are strongly recommended.

  • Place the driver device as close as possible to power and ground to minimize the length of high-current traces between the output pins and the gate of the power device.
  • Place the VCC bypass capacitors between the VCC pin and ground as close as possible to the driver with minimal trace length to improve the noise filtering. These capacitors support the high-peak current that is drawn from the VCC supply during turnon of the power MOSFET. The use of low inductance SM components such as chip resistors and chip capacitors is highly recommended.
  • The turnon and turnoff current-loop paths (driver device, power MOSFET, and VCC bypass capacitors) should be minimized as much as possible to keep the stray inductance to a minimum.
  • Separate power traces and signal traces, such as output and input signals.
  • Star-point grounding is a good way to minimize noise coupling from one current loop to another. The ground of the driver should be connected to the other circuit nodes such as the source of power switch, ground of PWM controller, and others at one single point. The connected paths should be as short as possible and as wide as possible to reduce resistance and inductance.
  • Use a ground plane to provide noise shielding. Fast rise and fall times at the OUT pin can corrupt the input signals during transition. The ground plane must not be a conduction path for any current loop. Instead, the ground plane must be connected to the star-point with one single trace to establish the ground potential.
  • A 1-Ω resistor may be connected between OUT pin and the gate terminal of the MOSFET to reduce gate to source voltage ringing.
  • A 20-Ω resistor should be connected between VD pin and the drain terminal of the MOSFET to limit the current flowing out of VD pin when the drain terminal voltage is negative.

11.2 Layout Example

UCD7138 layout_1_slvscs1.gifFigure 45. Layout Example With Surface-Mount MOSFET
UCD7138 layout_2_slvscs1.gifFigure 46. Layout Example With Through-Hole MOSFET