SLVSDD7B
August 2016 – March 2022
UCD9090A
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
I2C/Smbus/PMBus Timing Requirements
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
TI Fusion GUI
7.3.2
PMBus Interface
7.3.3
Rail Configuration
7.4
Device Functional Modes
7.4.1
Power Supply Sequencing
7.4.1.1
Turn-On Sequencing
7.4.1.2
Turn-Off Sequencing
7.4.1.3
Sequencing Configuration Options
7.4.2
Pin-Selected Rail States
7.4.3
Monitoring
7.4.3.1
Voltage Monitoring
7.4.3.2
Current Monitoring
7.4.3.3
Remote Temperature Monitoring and Internal Temperature Sensor
7.4.3.4
Temperature by Host Input
7.4.4
Fault Responses and Alert Processing
7.4.5
Shut Down All Rails and Sequence On (Resequence)
7.4.6
GPIOs
7.4.7
GPO Control
7.4.8
GPO Dependencies
7.4.8.1
GPO Delays
7.4.8.2
State Machine Mode Enable
7.4.9
GPI Special Functions
7.4.9.1
Fault Shutdown Rails
7.4.9.2
Configured as Sequencing Debug Pin
7.4.9.3
Configured as Fault Pin
7.4.9.4
Cold Boot Mode Enable
7.4.10
Power Supply Enables
7.4.11
Cascading Multiple Devices
7.4.12
PWM Outputs
7.4.12.1
FPWM1-8
7.4.12.2
PWM1-2
7.4.13
Programmable Multiphase PWMs
7.4.14
Margining
7.4.14.1
Open-Loop Margining
7.4.14.2
Closed-Loop Margining
7.4.15
Run Time Clock
7.4.16
System Reset Signal
7.4.17
Watch Dog Timer
7.4.18
Data and Error Logging to Flash Memory
7.4.19
Brownout Function
7.4.20
PMBus Address Selection
7.4.21
Device Reset
7.4.22
JTAG Interface
7.4.23
Internal Fault Management and Memory Error Correction (ECC)
7.5
Programming
7.5.1
Full Configuration Update While in Normal Mode
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Estimating ADC Reporting Accuracy
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Receiving Notification of Documentation Updates
11.3
Support Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RGZ|48
MPQF123F
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slvsdd7b_oa
slvsdd7b_pm
1
Features
Monitor and sequence 10 voltage rails
All rails sampled every 400 μs
12-bit ADC with 2.5-V, 0.5% internal V
REF
Sequence based on time, rail and pin dependencies
Four programmable undervoltage and overvoltage thresholds per monitor
Nonvolatile error and peak-value logging per monitor (up to 26 fault detail entries)
Closed-loop margining for 10 rails
Margin output adjusts rail voltage to match user-defined margin thresholds
Programmable watchdog timer and system reset
Flexible digital I/O configuration
Response and monitor to GPI-triggered fault
Easily cascade multiple power sequencers and take coordinated fault responses
Pin-selected rail states
Cascading multiple devices
Multiphase PWM clock generator
Clock frequencies from 15.259 kHz to
125 MHz
Capability to configure independent clock outputs for synchronizing switch-mode power supplies
JTAG and I
2
C/SMBus/
PMBus™
interfaces