SLES275A January   2015  – December 2017 VSP5324-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Dynamic Performance
    6. 6.6  Electrical Characteristics: General
    7. 6.7  Electrical Characteristics: Digital
    8. 6.8  Timing Requirements
    9. 6.9  LVDS Timing at Different Sampling Frequencies (One-Lane Interface, 12x Serialization)
    10. 6.10 LVDS Timing at Different Sampling Frequencies (Two-Lane Interface, 6x Serialization)
    11. 6.11 Serial Interface Timing Requirements
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Large- and Small-Signal Input Bandwidth
      2. 7.3.2 Digital Processing Block
        1. 7.3.2.1 Digital Gain
        2. 7.3.2.2 ADC Input Polarity Inversion
        3. 7.3.2.3 SYNC Function
        4. 7.3.2.4 Output Data Format
      3. 7.3.3 Serial LVDS Interface
        1. 7.3.3.1 One-Lane, 12x Serialization with DDR Bit Clock and 1x Frame Clock
        2. 7.3.3.2 Two-Lane, 6x Serialization with DDR Bit Clock and 0.5x Frame Clock
      4. 7.3.4 Bit Clock Programmability
      5. 7.3.5 LVDS Output Data and Clock Buffers
    4. 7.4 Device Functional Modes
      1. 7.4.1 External Reference Mode Of Operation
        1. 7.4.1.1 Using the REF Pins
        2. 7.4.1.2 Using the VCM Pin
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Register Initialization
      3. 7.5.3 Serial Register Readout
    6. 7.6 Register Maps
      1. 7.6.1 Serial Registers
        1. 7.6.1.1  Register 00h (offset = 00h) [reset = 0]
        2. 7.6.1.2  Register 01h (offset = 01h) [reset = 0]
        3. 7.6.1.3  Register 02h (offset = 02h) [reset = 0]
        4. 7.6.1.4  Register 0Ah (offset = 0Ah) [reset = 0]
        5. 7.6.1.5  Register 0Fh (offset = 0Fh) [reset = 0]
        6. 7.6.1.6  Register 14h (offset = 14h) [reset = 0]
        7. 7.6.1.7  Register 1Ch (offset = 1Ch) [reset = 0]
        8. 7.6.1.8  Register 23h (offset = 23h) [reset = 0]
        9. 7.6.1.9  Register 24h (offset = 24h) [reset = 0]
        10. 7.6.1.10 Register 25h (offset = 25h) [reset = 0]
        11. 7.6.1.11 Register 26h (offset = 26h) [reset = 0]
        12. 7.6.1.12 Register 27h (offset = 27h) [reset = 0]
        13. 7.6.1.13 Register 28h (offset = 28h) [reset = 0]
        14. 7.6.1.14 Register 29h (offset = 29h) [reset = 0]
        15. 7.6.1.15 Register 2Ah (offset = 2Ah) [reset = 0]
        16. 7.6.1.16 Register 2Bh (offset = 2Bh) [reset = 0]
        17. 7.6.1.17 Register 2Eh (offset = 2Eh) [reset = 0]
        18. 7.6.1.18 Register 30h (offset = 30h) [reset = 0]
        19. 7.6.1.19 Register 33h (offset = 33h) [reset = 0]
        20. 7.6.1.20 Register 35h (offset = 35h) [reset = 0]
        21. 7.6.1.21 Register 38h (offset = 38h) [reset = 0x0000]
        22. 7.6.1.22 Register 42h (offset = 42h) [reset = 0]
        23. 7.6.1.23 Register 45h (offset = 45h) [reset = 0]
        24. 7.6.1.24 Register 46h (offset = 46h) [reset = 0]
        25. 7.6.1.25 Register 50h (offset = 50h) [reset = 0]
        26. 7.6.1.26 Register 51h (offset = 51h) [reset = 0]
        27. 7.6.1.27 Register 53h (offset = 53h) [reset = 0]
        28. 7.6.1.28 Register 54h (offset = ) [reset = 0]
        29. 7.6.1.29 Register 55h (offset = 55h) [reset = 0]
        30. 7.6.1.30 Register F0h (offset = F0h) [reset = 0]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Drive Circuit Requirements
        2. 8.2.2.2 Clock Input
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General Guidelines
      2. 10.1.2 Grounding
      3. 10.1.3 Supply Decoupling
      4. 10.1.4 Exposed Pad
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

10.1.1 General Guidelines

The following list includes general layout guidelines. Refer to Figure 86 as needed.

  • Route the clock input as a differential pair when a differential clock input is used.
  • When single ended inputs are used, place 100-nF capacitors close to the pins on the INx_M inputs to ensure that the reference rail is stable. When differential inputs are used, the inputs must be routed as differential pairs.
  • Route the LVDS clock and data output pairs with 100-Ω differential impedance and length matched as per the sampling frequency.

10.1.2 Grounding

A single ground plane is sufficient to provide good performance, provided that the analog, digital, and clock sections of the board are cleanly partitioned.

10.1.3 Supply Decoupling

Minimal external decoupling can be used without loss in performance because the VSP5324-Q1 device already includes internal decoupling. Note that decoupling capacitors can help filter external power-supply noise, thus the optimum number of capacitors depends on the actual application. The decoupling capacitors should be placed very close to the converter supply pins.

10.1.4 Exposed Pad

In addition to providing a path for heat dissipation, the pad is also electrically connected to the digital ground internally. Therefore, soldering the exposed pad to the ground plane is necessary to achieve the best thermal and electrical performance. For detailed information, see application notes QFN Layout Guidelines and QFN/SON PCB Attachment.

10.2 Layout Example

VSP5324-Q1 layout_sles275.gif
The layout in this example uses four single-ended inputs and four LVDS-data outputs. The components that require special layout attention are shown and are listed in the General Guidelines section. For the two-lane output option, eight LVDS data pairs are used.
Figure 86. VSP5324-Q1 Layout Example