SLES275A January   2015  – December 2017 VSP5324-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Dynamic Performance
    6. 6.6  Electrical Characteristics: General
    7. 6.7  Electrical Characteristics: Digital
    8. 6.8  Timing Requirements
    9. 6.9  LVDS Timing at Different Sampling Frequencies (One-Lane Interface, 12x Serialization)
    10. 6.10 LVDS Timing at Different Sampling Frequencies (Two-Lane Interface, 6x Serialization)
    11. 6.11 Serial Interface Timing Requirements
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Large- and Small-Signal Input Bandwidth
      2. 7.3.2 Digital Processing Block
        1. 7.3.2.1 Digital Gain
        2. 7.3.2.2 ADC Input Polarity Inversion
        3. 7.3.2.3 SYNC Function
        4. 7.3.2.4 Output Data Format
      3. 7.3.3 Serial LVDS Interface
        1. 7.3.3.1 One-Lane, 12x Serialization with DDR Bit Clock and 1x Frame Clock
        2. 7.3.3.2 Two-Lane, 6x Serialization with DDR Bit Clock and 0.5x Frame Clock
      4. 7.3.4 Bit Clock Programmability
      5. 7.3.5 LVDS Output Data and Clock Buffers
    4. 7.4 Device Functional Modes
      1. 7.4.1 External Reference Mode Of Operation
        1. 7.4.1.1 Using the REF Pins
        2. 7.4.1.2 Using the VCM Pin
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Register Initialization
      3. 7.5.3 Serial Register Readout
    6. 7.6 Register Maps
      1. 7.6.1 Serial Registers
        1. 7.6.1.1  Register 00h (offset = 00h) [reset = 0]
        2. 7.6.1.2  Register 01h (offset = 01h) [reset = 0]
        3. 7.6.1.3  Register 02h (offset = 02h) [reset = 0]
        4. 7.6.1.4  Register 0Ah (offset = 0Ah) [reset = 0]
        5. 7.6.1.5  Register 0Fh (offset = 0Fh) [reset = 0]
        6. 7.6.1.6  Register 14h (offset = 14h) [reset = 0]
        7. 7.6.1.7  Register 1Ch (offset = 1Ch) [reset = 0]
        8. 7.6.1.8  Register 23h (offset = 23h) [reset = 0]
        9. 7.6.1.9  Register 24h (offset = 24h) [reset = 0]
        10. 7.6.1.10 Register 25h (offset = 25h) [reset = 0]
        11. 7.6.1.11 Register 26h (offset = 26h) [reset = 0]
        12. 7.6.1.12 Register 27h (offset = 27h) [reset = 0]
        13. 7.6.1.13 Register 28h (offset = 28h) [reset = 0]
        14. 7.6.1.14 Register 29h (offset = 29h) [reset = 0]
        15. 7.6.1.15 Register 2Ah (offset = 2Ah) [reset = 0]
        16. 7.6.1.16 Register 2Bh (offset = 2Bh) [reset = 0]
        17. 7.6.1.17 Register 2Eh (offset = 2Eh) [reset = 0]
        18. 7.6.1.18 Register 30h (offset = 30h) [reset = 0]
        19. 7.6.1.19 Register 33h (offset = 33h) [reset = 0]
        20. 7.6.1.20 Register 35h (offset = 35h) [reset = 0]
        21. 7.6.1.21 Register 38h (offset = 38h) [reset = 0x0000]
        22. 7.6.1.22 Register 42h (offset = 42h) [reset = 0]
        23. 7.6.1.23 Register 45h (offset = 45h) [reset = 0]
        24. 7.6.1.24 Register 46h (offset = 46h) [reset = 0]
        25. 7.6.1.25 Register 50h (offset = 50h) [reset = 0]
        26. 7.6.1.26 Register 51h (offset = 51h) [reset = 0]
        27. 7.6.1.27 Register 53h (offset = 53h) [reset = 0]
        28. 7.6.1.28 Register 54h (offset = ) [reset = 0]
        29. 7.6.1.29 Register 55h (offset = 55h) [reset = 0]
        30. 7.6.1.30 Register F0h (offset = F0h) [reset = 0]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Drive Circuit Requirements
        2. 8.2.2.2 Clock Input
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General Guidelines
      2. 10.1.2 Grounding
      3. 10.1.3 Supply Decoupling
      4. 10.1.4 Exposed Pad
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RGC Package
64-Pin VQFN With Exposed Thermal Pad
Top View
VSP5324-Q1 po_sles275.gif
NC - No internal connection

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
ADCLKM 24 Digital output Negative LVDS differential frame clock output pin
ADCLKP 23 Digital output Positive LVDS differential frame clock output pin
AGND 3 Ground Analog ground pin
6
9
37
40
43
46
AVDD 50 Supply Analog supply pin, 1.8 V
57
60
CLKM 59 Analog input Negative clock input
Differential clock input: apply differential clocks (sine wave, LVPECL, and LVDS) to CLKP and CLKM. Single-ended clock input: apply a CMOS clock to CLKP and tie CLKM to ground.
CLKP 58 Analog input Positive clock input
Differential clock input: apply differential clocks (sine wave, LVPECL, and LVDS) to CLKP and CLKM. Single-ended clock input: apply a CMOS clock to CLKP and tie CLKM to ground.
CS 61 Digital input Serial interface enable pin
IN1_M 2 Analog input Channel 1 negative differential analog input
IN1_P 1 Analog input Channel 1 positive differential analog input
IN2_M 8 Analog input Channel 2 negative differential analog input
IN2_P 7 Analog input Channel 2 positive differential analog input
IN3_M 42 Analog input Channel 3 negative differential analog input
IN3_P 41 Analog input Channel 3 positive differential analog input
IN4_M 48 Analog input Channel 4 negative differential analog input
IN4_P 47 Analog input Channel 4 positive differential analog input
INT/EXT 56 Digital input Internal and external reference control input pin
Logic high: device uses internal reference
Logic low: device uses external reference
LCLKM 26 Digital output Negative LVDS differential bit clock output pin
LCLKP 25 Digital output Positive LVDS differential bit clock output pin
LGND 12 Ground Digital ground pin
14
36
LVDD 35 Supply Digital and LVDS supply pin, 1.8 V
NC 4 — Unused; do not connect
5
10
11
38
39
44
45
51
OUT1A_M 16 Interface Channel 1A negative LVDS differential output pin.
This pin can be used with either one- or two-lane interface.
OUT1A_P 15 Interface Channel 1A positive LVDS differential output pin.
This pin can be used with either one- or two-lane interface.
OUT1B_M 18 Interface Channel 1B negative LVDS differential output pin. This pin is used with two-lane interface.
In one-lane interface, this pin is unused and must be floated without a 100-Ω termination.
OUT1B_P 17 Interface Channel 1B positive LVDS differential output pin. This pin is used with two-lane interface.
In one-lane interface, this pin is unused and must be floated without a 100-Ω termination.
OUT2A_M 20 Interface Channel 2A negative LVDS differential output pin.
This pin can be used with either one- or two-lane interface.
OUT2A_P 19 Interface Channel 2A positive LVDS differential output pin.
This pin can be used with either one- or two-lane interface.
OUT2B_M 22 Interface Channel 2B negative LVDS differential output pin. This pin is used with two-lane interface.
In one-lane interface, this pin is unused and must be floated without a 100-Ω termination.
OUT2B_P 21 Interface Channel 2B positive LVDS differential output pin. This pin is used with two-lane interface.
In one-lane interface, this pin is unused and must be floated without a 100-Ω termination.
OUT3A_M 30 Interface Channel 3A negative LVDS differential output pin.
This pin can be used with either one- or two-lane interface.
OUT3A_P 29 Interface Channel 3A positive LVDS differential output pin.
This pin can be used with either one- or two-lane interface.
OUT3B_M 28 Interface Channel 3B negative LVDS differential output pin. This pin is used with two-lane interface.
In one-lane interface, this pin is unused and must be floated without a 100-Ω termination.
OUT3B_P 27 Interface Channel 3B positive LVDS differential output pin. This pin is used with two-lane interface.
In one-lane interface, this pin is unused and must be floated without a 100-Ω termination.
OUT4A_M 34 Interface Channel 4A negative LVDS differential output pin.
This pin can be used with either one- or two-lane interface.
OUT4A_P 33 Interface Channel 4A positive LVDS differential output pin.
This pin can be used with either one- or two-lane interface.
OUT4B_M 32 Interface Channel 4B negative LVDS differential output pin. This pin is used with two-lane interface.
In one-lane interface, this pin is unused and must be floated without a 100-Ω termination.
OUT4B_P 31 Interface Channel 4B positive LVDS differential output pin. This pin is used with two-lane interface.
In one-lane interface, this pin is unused and must be floated without a 100-Ω termination.
PD 13 Digital input Power-down control input pin
Logic high: device is in power-down state; logic low: normal operation
REFB 54 Analog input Reference bottom voltage pin
Internal reference mode: the reference bottom voltage (0.45 V) is output on this pin.
External reference mode: the reference bottom voltage (0.45 V) must be externally applied to this pin. There are no required decoupling capacitors on this pin.
REFT 55 Analog input Reference top voltage pin
Internal reference mode: the reference top voltage (1.45 V) is output on this pin.
External reference mode: reference top voltage (1.45 V) must be externally applied to this pin. There are no required decoupling capacitors on this pin.
RESET 64 Digital input Serial interface reset pin; active low
SCLK 63 Digital input Serial interface clock pin
SDATA 62 Digital input Serial interface data pin
SDOUT 52 Digital output Serial interface readout pin
SYNC 49 Digital input Control input pin synchronizes test patterns across channels.
When unused, this pin should be tied to ground.
VCM 53 Analog output Common-mode voltage pin
Internal reference mode: common-mode voltage output pin, 0.95 V.
External reference mode: reference voltage must be externally applied to this pin.