SWRS245A December   2021  – February 2022 AM2732 , AM2732-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1. 3.1 Functional Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings - Automotive
    3. 7.3  Power-On Hours (POH)
      1. 7.3.1 Automotive Temperature Profile
      2. 7.3.2 Industrial Temperature Profile
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Operating Performance Points
    6. 7.6  Power Supply Specifications
    7. 7.7  I/O Buffer Type and Voltage Rail Dependency
    8. 7.8  CPU Specifications
    9. 7.9  Thermal Resistance Characteristics for nFBGA Package [ZCE285A]
    10. 7.10 Power Consumption Summary
    11. 7.11 Timing and Switching Characteristics
      1. 7.11.1 Power Supply Sequencing and Reset Timing
      2. 7.11.2 Clock Specifications
      3. 7.11.3 Peripheral Information
        1. 7.11.3.1  QSPI Flash Memory Peripheral
          1. 7.11.3.1.1 QSPI Timing Conditions
          2. 7.11.3.1.2 QSPI Timing Requirements
          3. 7.11.3.1.3 QSPI Switching Characteristics
        2. 7.11.3.2  MIBSPI Peripheral
          1. 7.11.3.2.1 SPI Timing Conditions
          2. 7.11.3.2.2 SPI Master Mode Timing and Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. 7.11.3.2.3 SPI Master Mode Timing and Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          4. 7.11.3.2.4 SPI Slave Mode Timing and Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        3. 7.11.3.3  Ethernet Switch (RGMII/RMII/MII) Peripheral
          1. 7.11.3.3.1  RGMII/GMII/MII Timing Conditions
          2. 7.11.3.3.2  RGMII Transmit Clock Switching Characteristics
          3. 7.11.3.3.3  RGMII Transmit Data and Control Switching Characteristics
          4. 7.11.3.3.4  RGMII Recieve Clock Timing Requirements
          5. 7.11.3.3.5  RGMII Recieve Data and Control Timing Requirements
          6. 7.11.3.3.6  RMII Transmit Clock Switching Characteristics
          7. 7.11.3.3.7  RMII Transmit Data and Control Switching Characteristics
          8. 7.11.3.3.8  RMII Receive Clock Timing Requirements
          9. 7.11.3.3.9  RMII Receive Data and Control Timing Requirements
          10. 7.11.3.3.10 MII Transmit Switching Characteristics
          11. 7.11.3.3.11 MII Receive Clock Timing Requirements
          12. 7.11.3.3.12 MII Receive Timing Requirements
          13. 7.11.3.3.13 MII Transmit Clock Timing Requirements
          14. 7.11.3.3.14 MDIO Interface Timings
        4. 7.11.3.4  LVDS/Aurora Instrumentation and Measurement Peripheral
          1. 7.11.3.4.1 LVDS Interface Configuration
          2. 7.11.3.4.2 LVDS Interface Timings
        5. 7.11.3.5  UART Peripheral
          1. 7.11.3.5.1 UART Timing Requirements
        6. 7.11.3.6  I2C Protocol Definition
          1. 7.11.3.6.1 I2C Timing Requirements (1)
        7. 7.11.3.7  Controller Area Network - Flexible Data-Rate (CAN-FD)
          1. 7.11.3.7.1 Dynamic Characteristics for the CAN-FD TX and RX Pins
        8. 7.11.3.8  CSI-2 Peripheral
        9. 7.11.3.9  General Purpose ADC (GPADC)
        10. 7.11.3.10 Enhanced Pulse-Width Modulator (ePWM)
        11. 7.11.3.11 Enhanced Capture (eCAP)
        12. 7.11.3.12 General-Purpose Input/Output
          1. 7.11.3.12.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) (1) (1)
      4. 7.11.4 Emulation and Debug
        1. 7.11.4.1 Emulation and Debug Description
        2. 7.11.4.2 JTAG Interface
          1. 7.11.4.2.1 Timing Requirements for IEEE 1149.1 JTAG
          2. 7.11.4.2.2 Switching Characteristics for IEEE 1149.1 JTAG
        3. 7.11.4.3 ETM Trace Interface
          1. 7.11.4.3.1 ETM TRACE Timing Requirements
          2. 7.11.4.3.2 ETM TRACE Switching Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Main Subsystem
    3. 8.3 DSP Subsystem
    4. 8.4 Radar Control Subsystem
    5. 8.5 Other Subsystems
      1. 8.5.1 Radar A2D Data Format Over CSI2 Interface
      2. 8.5.2 ADC Channels (Service) for User Application
    6. 8.6 Boot Modes
  9. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
      2. 9.1.2 Layout
        1. 9.1.2.1 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
      1. 10.1.1 Standard Package Symbolization
      2. 10.1.2 Device Naming Convention
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZCE|285
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

Processor Cores:

  • Dual-core Arm® Cortex®-R5F MCU subsystem operating up to 400 MHz, highly-integrated for real-time processing

    • Dual-core Arm® Cortex®-R5F cluster supports dual-core and single-core operation
    • 32KB ICache and 32KB DCache per R5F core with SECDED ECC on all memories
    • Single-core: 128KB TCM per cluster (128KB TCM per R5F core)
    • Dual-core: 128KB TCM per cluster (64KB TCM per R5F core)
  • TMS320C66x DSP core
    • Single core, 32-bit, floating point DSP
    • Operating at 450 MHz (14.4 GMAC)

Memory subsystem:

  • Up to 5.0 MB On Chip RAM (OCSRAM)
    • Memory space sharable between DSP, MCU, and shared L3
    • 3.5625MB shared L3 memory
    • 960KB dedicated to Main subsystem
    • 384KB dedicated to DSP subsystem
  • External Memory Interfaces (EMIF)
    • QSPI interface operating up to 67 MHz

System on Chip (SoC) Services and Architecture:

  • 12x EDMA for various subsystems, MCU, DSP and Accelerator cores
  • 5x Real-Time Interrupt (RTI) modules
  • Mailbox system for Interprocessor Communication (IPC)
  • JTAG/Trace interfaces for device debugging
  • Clock source
    • 40.0 MHz crystal with internal oscillator
    • Supports external oscillator at 40/50 MHz
    • Supports externally driven clock (Square/Sine) at 40/50 MHz

High-speed Serial Interfaces:

  • 10/100 Mbps Ethernet (RGMII/RMII/MII)
  • Input: 2x 4-lane MIPI D-PHY CSI 2.0 Data
  • Output: 4-lane Aurora/LVDS

General Connectivity Peripherals:

  • General Purpose Analog to Digital Converters (GPADC)
    • 1x 9-channel ADC supporting up to 625 Ksps
  • Digital Connectivity
    • 4x Serial Peripheral Interface (SPI) controllers operating up to 25 MHz
    • 3x Inter-Integrated Circuit (I2C) ports
    • 4x Universal Asynchronous Receiver-Transmitters (UART)

Industrial and control interfaces:

  • 3x Enhanced Pulse-Width Modulator (ePWM)
  • 1x Enhanced Capture Module (eCAP)
  • 2x Modular Controller Area Network (MCAN) modules with CAN-FD support

Power Management:

  • Simplified power sequencing and reduced number of power supply rails
  • Dual voltage digital I/O supporting 3.3V and 1.8V operation

Security:

  • Device Security
    • Programmable embedded Hardware Security Module (HSM)
    • Secure authenticated and encrypted boot support
    • Customer programmable root keys, symmetric keys (256 bit), Asymmetric keys (up to RSA-4K or ECC-512) with Key revocation capability
    • Crypto hardware accelerators - PKA with ECC, AES (up to 256 bit), TRNG/DRBG

Functional Safety:

  • Functional Safety-Compliant targeted
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 functional safety system design
    • Hardware integrity up to ASIL B targeted
    • Safety-related certification
      • ISO 26262 certification by TÜV SÜD planned
  • AEC-Q100 qualification targeted
  • Operating Conditions
    • Automotive grade temperature range supported
    • Industrial grade temperature range supported

Package options:

  • ZCE (285-pin) nFBGA package 13mm x 13mm, 0.65 mm pitch
  • 45-nm technology
  • Compact solution size