JAJSRW8 November   2023 ADC34RF55

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics - Power Consumption
    6. 5.6  Electrical Characteristics - DC Specifications
    7. 5.7  Electrical Characteristics - AC Specifications (Dither DISABLED)
    8. 5.8  Electrical Characteristics - AC Specifications (Dither ENABLED)
    9. 5.9  Timing Requirements
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
        1. 6.3.1.1 Input Bandwidth and Full-Scale
        2. 6.3.1.2 Input Imbalance
        3. 6.3.1.3 Over Range Indication
        4. 6.3.1.4 Analog out-of-band dither
      2. 6.3.2 Sampling Clock Input
      3. 6.3.3 ADC Foreground Calibration
        1. 6.3.3.1 Calibration Control
        2. 6.3.3.2 ADC Switch
        3. 6.3.3.3 Calibration Configuration
      4. 6.3.4 SYSREF
        1. 6.3.4.1 SYSREF Capture Detection
      5. 6.3.5 Decimation Filter
        1. 6.3.5.1 Decimation Filter Response
        2. 6.3.5.2 Decimation Filter Configuration
        3. 6.3.5.3 20-bit Output Mode
        4. 6.3.5.4 Numerically Controlled Oscillator (NCO)
        5. 6.3.5.5 NCO Frequency Programming Using the SPI Interface
        6. 6.3.5.6 Fast Frequency Hopping
          1. 6.3.5.6.1 Fast frequency hopping using the GPIO1/2 pins
          2. 6.3.5.6.2 Fast frequency hopping using GPIO1/2, SEN and SDATA pins
          3. 6.3.5.6.3 Fast frequency hopping using the fast SPI
      6. 6.3.6 JESD204B Interface
        1. 6.3.6.1 JESD204B Initial Lane Alignment (ILA)
          1. 6.3.6.1.1 SYNC Signal
        2. 6.3.6.2 JESD204B Frame Assembly
          1. 6.3.6.2.1 JESD204B Frame Assembly in Bypass Mode
          2. 6.3.6.2.2 JESD204B Frame Assembly with Real Decimation - Single Band
          3. 6.3.6.2.3 JESD204B Frame Assembly with Complex Decimation - Single Band
          4. 6.3.6.2.4 JESD204B Frame Assembly with Decimation - Dual Band
        3. 6.3.6.3 SERDES Output MUX
      7. 6.3.7 Test Pattern
        1. 6.3.7.1 Transport Layer
        2. 6.3.7.2 Link Layer
        3. 6.3.7.3 Internal Capture Memory Buffer
    4. 6.4 Device Functional Modes
      1. 6.4.1 Bypass Mode
      2. 6.4.2 Digital Averaging
    5. 6.5 Programming
      1. 6.5.1 GPIO Pin Control
      2. 6.5.2 Configuration using the SPI interface
        1. 6.5.2.1 Register Write
        2. 6.5.2.2 Register Read
    6. 6.6 Register Maps
      1. 6.6.1 Detailed Register Description
  8. 7 Application Information Disclaimer
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Wideband RF Sampling Receiver
      2. 7.2.2 Design Requirements
        1. 7.2.2.1 Input Signal Path
        2. 7.2.2.2 Clocking
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Sampling Clock
      4. 7.2.4 Application Curves
    3. 7.3 Initialization Set Up
      1. 7.3.1 Initial Device Configuration After Power-Up
        1. 7.3.1.1  STEP 1: RESET
        2. 7.3.1.2  STEP 2: Device Configuration
        3. 7.3.1.3  STEP 3: JESD Interface Configuration (1)
        4. 7.3.1.4  STEP 4: SYSREF Synchronization
        5. 7.3.1.5  STEP 5: JESD Interface Configuration (2)
        6. 7.3.1.6  STEP 6: Analog Trim Settings
        7. 7.3.1.7  STEP 7: Calibration Configuration
        8. 7.3.1.8  STEP 8: SYSREF Synchronization
        9. 7.3.1.9  STEP 9: Run Power up Calibration
        10. 7.3.1.10 Step 10: JESD Interface Synchronization
        11. 7.3.1.11 Step 11: NCO Configuration
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 デバイスのサポート
      1. 8.1.1 サード・パーティ製品に関する免責事項
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.7 Electrical Characteristics - AC Specifications (Dither DISABLED)

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, ADC sampling rate = 2.6 GSPS, 8x complex decimation single band, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, AVDDCLK, DVDD = 1.2 V, –1-dBFS differential input and dither DISABLED, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
NSD Noise Spectral Density fIN = 900 MHz, AIN = -20 dBFS
no averaging		 –155.6 dBFS/Hz
fIN = 900 MHz, AIN = -20 dBFS
2x averaging		 –158.1
NF Noise Figure fIN = 900 MHz, Ain = -20 dBFS, no averaging 20.2 dB
fIN = 900 MHz, Ain = -20 dBFS, 2x averaging 19.8 dB
SNR Signal-to-noise ratio
no averaging
(DDC bypass characterization mode)		 fIN = 100 MHz 62.1 dBFS
fIN = 500 MHz 61.8
fIN = 900 MHz 61.7
fIN = 900  MHz, Ain = -20 dBFS 63.8
fIN = 1.8 GHz 61.1
fIN = 2.4 GHz 60.2
Signal-to-noise ratio
no averaging
8x complex decimation		 fIN = 500 MHz 68.5
fIN = 900 MHz 68.0
fIN = 900  MHz, Ain = -20 dBFS 69.4
fIN = 1.8 GHz 66.6
fIN = 2.4 GHz 66.0
Signal-to-noise ratio
2x averaging
(DDC bypass characterization mode)		 fIN = 100 MHz 63.6
fIN = 500 MHz 63.3
fIN = 900 MHz 63.5
fIN = 900  MHz, Ain = -20 dBFS 66.3
fIN = 1.8 GHz 62.7
fIN = 2.4 GHz 62.4
Signal-to-noise ratio
2x averaging
8x complex decimation		 fIN = 500 MHz 69.7
fIN = 900 MHz 68.0
fIN = 900  MHz, Ain = -20 dBFS 69.5
fIN = 1.8 GHz 67.4
fIN = 2.4 GHz 67.0
SINAD(1) Signal to noise and distortion ratio
(DDC bypass characterization mode)		 fIN = 100 MHz 58.2 dBFS
fIN = 500 MHz 57.9
fIN = 900 MHz 55.8
fIN = 1.8 GHz 58.2
fIN = 2.4 GHz 54.8
ENOB(1) Effective number of bits
(DDC bypass characterization mode)		 fIN = 100 MHz 10.0 Bits
fIN = 500 MHz 10.0
fIN = 900 MHz 10.0
fIN = 1.8 GHz 9.9
fIN = 2.4 GHz 9.7
THD(1) Total Harmonic Distortion (First five harmonics)
(DDC bypass characterization mode)		 fIN = 100 MHz 61 dBc
fIN = 500 MHz 60
fIN = 900 MHz 57
fIN = 1.8 GHz 63
fIN = 2.4 GHz 57
HD2(1) Second Harmonic Distortion
(DDC bypass characterization mode)		 fIN = 100 MHz 61 dBc
fIN = 500 MHz 66
fIN = 900 MHz 68
fIN = 1.8 GHz 66
fIN = 2.4 GHz 57
HD3(1) Third Harmonic Distortion
(DDC bypass characterization mode)		 fIN = 100 MHz 66 dBc
fIN = 500 MHz 62
fIN = 900 MHz 57
fIN = 1.8 GHz 65
fIN = 2.4 GHz 64
Non HD2,3(1) Spur free dynamic range (excluding HD2 and HD3)
(DDC bypass characterization mode)		 fIN = 100 MHz 78 dBFS
fIN = 500 MHz 75
fIN = 900 MHz 78
fIN = 1.8 GHz 76
fIN = 2.4 GHz 75
IMD3(1) Two tone inter-modulation distortion f1 = 700 MHz, f2 = 800 MHz, AIN = -7 dBFS/tone 72 dBFS
f1 = 1.5 GHz, f2 = 1.6 GHz, AIN = -7 dBFS/tone 66
(1) Performance data shown is prior to decimation filtering. With DDC enabled, performance improves by the decimation filtering process.