A global power down mode can be enabled via SPI as well as using the power down pin (PDN/SYNC). There is an internal pull-down 21 kΩ resistor on the PDN/SYNC input pin and the pin is active high - so the pin needs to be pulled high externally to enter global power down mode.
The SPI register map provides the capability to enable/disable individual blocks directly or via PDN pin mask in order to trade off power consumption vs wake up time as shown in Table 8-11.
|Function/ Register||PDN |
|Mask for |
|Feature - Default||Power|
|ADC||Yes||-||Enabled||Both ADC channels are included in Global PDN automatically|
|Reference gain amplifier||Yes||Yes||Enabled||~ 0.4 mA||~3 us||Should only be powered down in power down state.|
|Internal 1.2 V reference||Yes||External ref||~ 1-3.5 mA||~3 ms||Internal/external reference selection is available through SPI and REFBUF pin.|
|Clock buffer||Yes||Differential clock||~ 1 mA||n/a||Single ended clock input saves ~ 1mA compared to differential. |
Some programmability is available through the REFBUF pin.
|Output interface drivers||Yes||-||Enabled||varies||n/a||Depending on output interface mode, unused output drivers can be powered down for maximum power savings|
|Decimation filter||Yes||-||Disabled||see electrical table||n/a|