In this mode the output data is serialized and transmitted over 2, 1 or 1/2 wires. Due to CMOS output speed limitation this mode is only available for reduced output data rates. This mode is similar to the multi-SPI interface.
In this operating mode, the ADC364x requires an external serial clock input (DCLKIN), which is used to transmit the data out of the ADC along with the data clock (DCLK). The phase relationship between DCLKIN and the sampling clock is irrelevant but both clocks need to be frequency locked. The serial CMOS interface is configured using SPI register writes.