JAJSOX0 March 2024 ADS127L18
ADVANCE INFORMATION
The ADC provides the option of an external clock input. In the hardware programming mode, operation is fixed to the external clock input. In SPI programming mode, the external clock mode is selected by applying the clock signal to the CLKIN pin. The CLK_SEL bit is then programmed to 1b. If necessary, program the ADC clock divider to configure the ADC clock frequency appropriate to the speed mode. For example, divide a 25.6MHz clock input frequency by 8 to configure the clock frequency to 3.2MHz for the low-speed mode. This configuration allows the DCLK frequency of the FSYNC data port to operate at 25.6MHz.
Decrease the clock frequency from the nominal frequency to yield specific data rates between the programmable OSR values. When doing so, the conversion noise at the new frequency is the same as the original frequency. Reducing the conversion noise is only possible by increasing the OSR value or changing the speed or filter modes.
Clock jitter results in timing variations of the modulator sampling that leads to degraded SNR performance. A low-jitter clock is essential to meet data sheet SNR performance. For example, with a 200kHz signal frequency, an external clock with < 10ps (rms) jitter is required. For lower signal frequencies, the clock jitter is relaxed by –20dB per decade of signal frequency reduction. For example, with fIN = 20kHz, a clock with 100ps jitter is acceptable. Many types of RC oscillators exhibit high levels of jitter that are to be avoided for ac signal measurement. Instead, use a crystal oscillator or low-jitter integrated circuit oscillator clock sources. Avoid ringing at the clock input. A series resistor placed at the output of the clock buffer often helps reduce ringing.