JAJSOX0 March   2024 ADS127L18

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Internal Oscillator
        2. 7.3.3.2 External Clock
      4. 7.3.4 Power Supplies
        1. 7.3.4.1 AVDD1 and AVSS
        2. 7.3.4.2 AVDD2
        3. 7.3.4.3 IOVDD
        4. 7.3.4.4 Power-On Reset (POR)
        5. 7.3.4.5 CAPA and CAPD
      5. 7.3.5 VCM Output Voltage
      6. 7.3.6 GPIO
      7. 7.3.7 Modulator
      8. 7.3.8 Digital Filter
        1. 7.3.8.1 Wideband Filter
      9. 7.3.9 Low-Latency Filter (Sinc)
        1. 7.3.9.1 Sinc4 Filter
        2. 7.3.9.2 Sinc4 + Sinc1 Cascade Filter
        3. 7.3.9.3 Sinc3 Filter
        4. 7.3.9.4 Sinc3 + Sinc1 Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1  Speed Modes
      2. 7.4.2  Synchronization
        1. 7.4.2.1 Synchronized Control Mode
        2. 7.4.2.2 Start/Stop Control Mode
      3. 7.4.3  Digital Filter Settling
      4. 7.4.4  Conversion-Start Delay Time
      5. 7.4.5  Data Averaging
      6. 7.4.6  Calibration
        1. 7.4.6.1 Offset Calibration Registers
        2. 7.4.6.2 Gain Calibration Registers
        3. 7.4.6.3 Calibration Procedure
      7. 7.4.7  Reset
        1. 7.4.7.1 RESET Pin
        2. 7.4.7.2 Reset by SPI Register
        3. 7.4.7.3 Reset by SPI Input Pattern
      8. 7.4.8  Power-Down
      9. 7.4.9  Idle and Standby Modes
      10. 7.4.10 Diagnostics
        1. 7.4.10.1 ERROR Pin and ERR_FLAG Bit
        2. 7.4.10.2 Clock Counter
        3. 7.4.10.3 SCLK Counter
        4. 7.4.10.4 Frame-Sync CRC
        5. 7.4.10.5 SPI CRC
        6. 7.4.10.6 Register Map CRC
        7. 7.4.10.7 Self Test
      11. 7.4.11 Frame-Sync Data Port
        1. 7.4.11.1 FSYNC Pin
        2. 7.4.11.2 DCLK Pin
        3. 7.4.11.3 DOUTn Pins
        4. 7.4.11.4 DINn Pins
        5. 7.4.11.5 Time Division Multiplexing (TDM)
        6. 7.4.11.6 Data Size
        7. 7.4.11.7 STATUS_DP Header
        8. 7.4.11.8 Daisy Chain
        9. 7.4.11.9 Data Port Offset Timing
    5. 7.5 Programming
      1. 7.5.1 Hardware Programming
      2. 7.5.2 SPI Programming
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output (SDO)
      3. 7.5.3 SPI Frame
      4. 7.5.4 SPI Commands
        1. 7.5.4.1 Read Register Command
        2. 7.5.4.2 Write Register Command
      5. 7.5.5 SPI Daisy-Chain
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Driver
      2. 9.1.2 Antialias Filter
      3. 9.1.3 Reference Voltage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.8.1 Wideband Filter

The wideband filter is a multistage FIR design featuring linear phase response, low pass-band ripple, narrow transition band, and high stop-band attenuation. Because of these characteristics, the filter is designed for measuring ac and dc signals. The ADC provides eight programmable values of OSR and four speed modes, offering a range of data rate, resolution and data rate options.

Figure 7-12 through Figure 7-16 illustrate the frequency response of the wideband filter. Figure 7-12 shows the pass-band ripple. Figure 7-13 shows the detailed frequency response at the transition band.

GUID-20201006-CA0I-WVMP-H84L-06HR4S54JSXP-low.gif
 
Figure 7-12 Wideband Filter Pass-Band Ripple
GUID-20201006-CA0I-CLXP-2CSG-SR2JZ8Q6LDVM-low.gif
 
Figure 7-13 Wideband Filter Transition Band

Figure 7-14 shows the frequency response to fDATA for OSR ≥ 64. The stop band begins at fDATA / 2 to prevent aliasing at the Nyquist frequency. Figure 7-15 shows the stop-band attenuation to fMOD for OSR = 32. In the stop-band region, out-of-band input frequencies mix with multiples of the fMOD / 32 chop frequency. This process creates a pattern of stop-band response peaks that exceed the attenuation provided by the digital filter. The width of the response peaks is twice the filter bandwidth. Stop-band attenuation is improved when used in conjunction with an antialias filter at the ADC input.

GUID-20201006-CA0I-TJTC-PQG1-NQMZLTMTQTGT-low.gif
OSR ≥ 64
Figure 7-14 Wideband Filter Frequency Response
GUID-20211026-SS0I-DGBX-7JGM-RBSWG9HQJF3L-low.svg
OSR = 32
Figure 7-15 Wideband Filter Stop-Band

Figure 7-16 shows the filter response centered at fMOD, where the filter response repeats. If not removed by an antialiasing filter, input frequencies at fMOD appear as aliased frequencies in the pass band. Aliasing also occurs by input frequencies occurring at multiples of fMOD. These frequency bands are defined by:

Equation 18. Alias frequency bands: (N · fMOD) ± fBW

where:

  • N = 1, 2, 3, and so on
  • fMOD = Modulator sampling frequency
  • fBW = Filter bandwidth

GUID-20201006-CA0I-PHMH-L45N-8ZXNGWPMQPHW-low.svg
 
Figure 7-16 Wideband Filter Frequency Response Centered at fMOD

The group delay of the filter is the time for a signal to propagate from the input to the output of the filter. Because the filter is a linear-phase design, the envelope of a multifrequency complex signal is undistorted by filter processing. The group delay (expressed in units of time) is constant versus signal frequency and is equal to 34 / fDATA. Be aware that after a step input is applied to the ADC inputs, fully settled data occurs 68 data periods later. Figure 7-17 shows the filter group delay (34 / fDATA) and the settling time for a step input (68 / fDATA).

GUID-20201012-CA0I-JZT5-BMLL-HTPHNMQKFVTV-low.svg
 
Figure 7-17 Wideband Filter Step Response

The digital filter is restarted when the ADC is synchronized. After synchronization, the ADC either discards 68 conversion results to account for filter settling, or immediately outputs unsettled data. The DP_MODE bit the DP_CFG1 register selects the option used. In settled-data mode, there is no need to discard data. The Latency Time column of Table 7-9 lists the time for the first data to appear. If a step input occurs asynchronous to the conversion period, then the next 69 conversions are partially settled data.

Table 7-4 Wideband Filter Characteristics
MODE fCLK
(MHz)		 OSR DATA RATE
(kSPS)		 –0.1dB FREQUENCY
(kHz)		 –3dB FREQUENCY
(kHz)		 LATENCY TIME1
(µs)
Max speed 32.768 32 512 211.2 223.9 133.2
High speed 25.6 400 165 174.96 170.6
Mid speed 12.8 200 82.5 87.48 341.2
Low speed 3.2 50 20.63 21.87 1364.8
Max speed 32.768 64 256 105.6 112.0 266.0
High speed 25.6 200 82.5 87.48 340.6
Mid speed 12.8 100 41.25 43.74 681.2
Low speed 3.2 25 10.31 10.94 2724.8
Max speed 32.768 128 128 52.8 55.99 531.6
High speed 25.6 100 41.25 43.74 680.6
Mid speed 12.8 50 20.63 21.87 1361.2
Low speed 3.2 12.5 5.1562 5.468 5444.8
Max speed 32.768 256 64 26.4 28.00 1062.87
High speed 25.6 50 20.625 21.87 1360.6
Mid speed 12.8 25 10.31 10.93 2721.2
Low speed 3.2 6.25 2.578 2.734 10884.8
Max speed 32.768 512 32 13.2 14.00 2125.37
High speed 25.6 25 10.312 10.935 2720.6
Mid speed 12.8 12.5 5.156 5.467 5441.2
Low speed 3.2 3.125 1.289 1.367 21764.8
Max speed 32.768 1024 16 6.6 7.998 4250.4
High speed 25.6 12.5 5.156 5.467 5440.6
Mid speed 12.8 6.25 2.578 2.734 10881.2
Low speed 3.2 1.5625 0.645 0.6834 43524.8
Max speed 32.768 2048 8 3.3 3.499 8500.4
High speed 25.6 6.25 2.578 2.734 10880.6
Mid speed 12.8 3.125 1.289 1.367 21761.2
Low speed 3.2 0.78125 0.322 0.3417 87044.8
Max speed 32.768 4096 4 1.65 1.750 17000.4
High speed 25.6 3.125 1.289 1.367 21760.6
Mid speed 12.8 1.5625 0.645 0.6834 43521.1
Low speed 3.2 0.390625 0.161 0.1709 174084.8
(1) Latency time increases by 8 / fCLK (µs) when the analog input buffers are enabled.