JAJSGA0A
September 2018 – August 2019
ADS1284
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
概略回路図
4
改訂履歴
5
概要(続き)
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements
7.7
Switching Characteristics
7.8
Typical Characteristics
8
Parameter Measurement Information
8.1
Noise Performance
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Analog Inputs and Multiplexer
9.3.2
Programmable Gain Amplifier (PGA)
9.3.3
Analog-to-Digital Converter (ADC)
9.3.3.1
Modulator
9.3.3.1.1
Modulator Overrange
9.3.3.1.2
Modulator Input Impedance
9.3.3.1.3
Modulator Overrange Detection (MFLAG)
9.3.3.1.4
Offset
9.3.3.1.5
Voltage Reference Inputs (VREFP, VREFN)
9.3.3.2
Digital Filter
9.3.3.2.1
Sinc Filter Section (sinx / x)
9.3.3.2.2
FIR Section
9.3.3.2.3
Group Delay and Step Response
9.3.3.2.3.1
Linear Phase Response
9.3.3.2.3.2
Minimum Phase Response
9.3.3.2.4
HPF Section
9.4
Device Functional Modes
9.4.1
Synchronization (SYNC PIN and SYNC Command)
9.4.1.1
Pulse-Sync Mode
9.4.1.2
Continuous-Sync Mode
9.4.2
Reset (RESET Pin and Reset Command)
9.4.3
Master Clock Input (CLK)
9.4.4
Power-Down (PWDN Pin and STANDBY Command)
9.4.5
Power-On Sequence
9.4.6
DVDD Power Supply
9.4.7
Serial Interface
9.4.7.1
Chip Select (CS)
9.4.7.2
Serial Clock (SCLK)
9.4.7.3
Data Input (DIN)
9.4.7.4
Data Output (DOUT)
9.4.7.5
Serial Port Auto Timeout
9.4.7.6
Data Ready (DRDY)
9.4.8
Data Format
9.4.9
Reading Data
9.4.9.1
Read-Data-Continuous Mode
9.4.9.2
Read-Data-By-Command Mode
9.4.10
One-Shot Operation
9.4.11
Offset and Full-Scale Calibration Registers
9.4.11.1
OFC[2:0] Registers
9.4.11.2
FSC[2:0] Registers
9.4.12
Calibration Commands (OFSCAL and GANCAL)
9.4.12.1
OFSCAL Command
9.4.12.2
GANCAL Command
9.4.13
User Calibration
9.5
Programming
9.5.1
Commands
9.5.1.1
SDATAC Requirements
9.5.1.2
WAKEUP: Wake-Up From Standby Mode
9.5.1.3
STANDBY: Standby Mode
9.5.1.4
SYNC: Synchronize the Analog-to-Digital Conversion
9.5.1.5
RESET: Reset the Device
9.5.1.6
RDATAC: Read Data Continuous
9.5.1.7
SDATAC: Stop Read Data Continuous
9.5.1.8
RDATA: Read Data by Command
9.5.1.9
RREG: Read Register Data
9.5.1.10
WREG: Write to Register
9.5.1.11
OFSCAL: Offset Calibration
9.5.1.12
GANCAL: Gain Calibration
9.6
Register Maps
9.6.1
Register Descriptions
9.6.1.1
ID_CFG: ID_Configuration Register (address = 00h) [reset =x0h]
9.6.1.2
CONFIG0: Configuration Register 0 (address = 01h) [reset = 52h]
9.6.1.3
CONFIG1: Configuration Register 1 (address = 02h) [reset = 08h]
9.6.1.4
HPF0 and HPF1 Registers
9.6.1.4.1
HPF0: High-Pass Filter Corner Frequency, Low Byte (address = 03h) [reset = 32h]
9.6.1.4.2
HPF1: High-Pass Filter Corner Frequency, High Byte (address = 04h) [reset = 03h]
9.6.1.5
OFC0, OFC1, OFC2 Registers
9.6.1.5.1
OFC0: Offset Calibration, Low Byte (address = 05h) [reset = 00h]
9.6.1.5.2
OFC1: Offset Calibration, Mid Byte (address = 06h) [reset = 00h]
9.6.1.5.3
OFC2: Offset Calibration, High Byte (address = 07h) [reset = 00h]
9.6.1.6
FSC0, FSC1, FSC2 Registers
9.6.1.6.1
FSC0: Full-Scale Calibration, Low Byte (address = 08h) [reset = 00h]
9.6.1.6.2
FSC1: Full-Scale Calibration, Mid Byte (address = 09h) [reset = 00h]
9.6.1.6.3
FSC2: Full-Scale Calibration, High Byte (address = 0Ah) [reset = 40h]
10
Application and Implementation
10.1
Application Information
10.2
Typical Applications
10.2.1
Geophone Interface
10.2.2
Digital Interface
10.3
Initialization Set Up
11
デバイスおよびドキュメントのサポート
11.1
ドキュメントの更新通知を受け取る方法
11.2
コミュニティ・リソース
11.3
商標
11.4
静電気放電に関する注意事項
11.5
Glossary
12
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RHF|24
MPQF137H
サーマルパッド・メカニカル・データ
発注情報
jajsga0a_oa
7.8
Typical Characteristics
At +25°C, AVDD = 2.5 V, AVSS = –2.5 V, f
CLK
= 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, PGA = 1, High-Resolution Mode, OFFSET enabled, CHOP enabled, and f
DATA
= 1000 SPS (unless otherwise noted).
Figure 2.
Output Spectrum
Figure 4.
Output Spectrum
Figure 6.
Output Spectrum
Figure 8.
Output Spectrum
Figure 10.
Output Spectrum
Figure 12.
Output Spectrum
Figure 14.
Output Spectrum
Figure 16.
THD vs Temperature
Figure 18.
THD vs Signal Frequency
Figure 20.
PSR vs Power-Supply Frequency
Figure 22.
Offset-Voltage Drift Histogram
Figure 24.
Gain-Error Drift Histogram
Figure 26.
SNR vs Temperature
Figure 28.
Crosstalk Output Spectrum
Figure 30.
Input Bias Current vs Input Voltage
Figure 32.
Reference Input Impedance vs Temperature
Figure 3.
Output Spectrum (Low-Power mode)
Figure 5.
Output Spectrum (Low-Power Mode)
Figure 7.
Output Spectrum (Low-Power Mode)
Figure 9.
Output Spectrum (Low-Power Mode)
Figure 11.
Output Spectrum (Low-Power Mode)
Figure 13.
Output Spectrum (Low-Power Mode)
Figure 15.
Output Spectrum
Figure 17.
THD vs Temperature (Low-Power Mode)
Figure 19.
CMR vs Common-Mode Frequency
Figure 21.
Offset-Voltage Histogram
Figure 23.
Gain-Error Histogram
Figure 25.
Gain-Match Histogram
Figure 27.
SNR vs Temperature (Low-Power Mode)
Figure 29.
Power vs Temperature
Figure 31.
Input Bias Current vs Input Voltage