JAJSGA0A September   2018  – August 2019 ADS1284

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Inputs and Multiplexer
      2. 9.3.2 Programmable Gain Amplifier (PGA)
      3. 9.3.3 Analog-to-Digital Converter (ADC)
        1. 9.3.3.1 Modulator
          1. 9.3.3.1.1 Modulator Overrange
          2. 9.3.3.1.2 Modulator Input Impedance
          3. 9.3.3.1.3 Modulator Overrange Detection (MFLAG)
          4. 9.3.3.1.4 Offset
          5. 9.3.3.1.5 Voltage Reference Inputs (VREFP, VREFN)
        2. 9.3.3.2 Digital Filter
          1. 9.3.3.2.1 Sinc Filter Section (sinx / x)
          2. 9.3.3.2.2 FIR Section
          3. 9.3.3.2.3 Group Delay and Step Response
            1. 9.3.3.2.3.1 Linear Phase Response
            2. 9.3.3.2.3.2 Minimum Phase Response
          4. 9.3.3.2.4 HPF Section
    4. 9.4 Device Functional Modes
      1. 9.4.1  Synchronization (SYNC PIN and SYNC Command)
        1. 9.4.1.1 Pulse-Sync Mode
        2. 9.4.1.2 Continuous-Sync Mode
      2. 9.4.2  Reset (RESET Pin and Reset Command)
      3. 9.4.3  Master Clock Input (CLK)
      4. 9.4.4  Power-Down (PWDN Pin and STANDBY Command)
      5. 9.4.5  Power-On Sequence
      6. 9.4.6  DVDD Power Supply
      7. 9.4.7  Serial Interface
        1. 9.4.7.1 Chip Select (CS)
        2. 9.4.7.2 Serial Clock (SCLK)
        3. 9.4.7.3 Data Input (DIN)
        4. 9.4.7.4 Data Output (DOUT)
        5. 9.4.7.5 Serial Port Auto Timeout
        6. 9.4.7.6 Data Ready (DRDY)
      8. 9.4.8  Data Format
      9. 9.4.9  Reading Data
        1. 9.4.9.1 Read-Data-Continuous Mode
        2. 9.4.9.2 Read-Data-By-Command Mode
      10. 9.4.10 One-Shot Operation
      11. 9.4.11 Offset and Full-Scale Calibration Registers
        1. 9.4.11.1 OFC[2:0] Registers
        2. 9.4.11.2 FSC[2:0] Registers
      12. 9.4.12 Calibration Commands (OFSCAL and GANCAL)
        1. 9.4.12.1 OFSCAL Command
        2. 9.4.12.2 GANCAL Command
      13. 9.4.13 User Calibration
    5. 9.5 Programming
      1. 9.5.1 Commands
        1. 9.5.1.1  SDATAC Requirements
        2. 9.5.1.2  WAKEUP: Wake-Up From Standby Mode
        3. 9.5.1.3  STANDBY: Standby Mode
        4. 9.5.1.4  SYNC: Synchronize the Analog-to-Digital Conversion
        5. 9.5.1.5  RESET: Reset the Device
        6. 9.5.1.6  RDATAC: Read Data Continuous
        7. 9.5.1.7  SDATAC: Stop Read Data Continuous
        8. 9.5.1.8  RDATA: Read Data by Command
        9. 9.5.1.9  RREG: Read Register Data
        10. 9.5.1.10 WREG: Write to Register
        11. 9.5.1.11 OFSCAL: Offset Calibration
        12. 9.5.1.12 GANCAL: Gain Calibration
    6. 9.6 Register Maps
      1. 9.6.1 Register Descriptions
        1. 9.6.1.1 ID_CFG: ID_Configuration Register (address = 00h) [reset =x0h]
        2. 9.6.1.2 CONFIG0: Configuration Register 0 (address = 01h) [reset = 52h]
        3. 9.6.1.3 CONFIG1: Configuration Register 1 (address = 02h) [reset = 08h]
        4. 9.6.1.4 HPF0 and HPF1 Registers
          1. 9.6.1.4.1 HPF0: High-Pass Filter Corner Frequency, Low Byte (address = 03h) [reset = 32h]
          2. 9.6.1.4.2 HPF1: High-Pass Filter Corner Frequency, High Byte (address = 04h) [reset = 03h]
        5. 9.6.1.5 OFC0, OFC1, OFC2 Registers
          1. 9.6.1.5.1 OFC0: Offset Calibration, Low Byte (address = 05h) [reset = 00h]
          2. 9.6.1.5.2 OFC1: Offset Calibration, Mid Byte (address = 06h) [reset = 00h]
          3. 9.6.1.5.3 OFC2: Offset Calibration, High Byte (address = 07h) [reset = 00h]
        6. 9.6.1.6 FSC0, FSC1, FSC2 Registers
          1. 9.6.1.6.1 FSC0: Full-Scale Calibration, Low Byte (address = 08h) [reset = 00h]
          2. 9.6.1.6.2 FSC1: Full-Scale Calibration, Mid Byte (address = 09h) [reset = 00h]
          3. 9.6.1.6.3 FSC2: Full-Scale Calibration, High Byte (address = 0Ah) [reset = 40h]
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Geophone Interface
      2. 10.2.2 Digital Interface
    3. 10.3 Initialization Set Up
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.3.1.4 Offset

The modulator can produce low-level idle tones that appear in the conversion data when there is no signal input or when low-level signal inputs are present to the ADC. The ADC provides an optional dc offset voltage designed to shift the idle tones to the stop band of digital filter response, where the idle tones are reduced. The internal offset is applied at the modulator input; therefore, the offset voltage is independent of PGA gain. Two offset voltage options are provided, 75 mV and 100 mV. The 75-mV offset is more effective to reduce idle tones under various gain, data rate, and chop mode settings.

The offset is enabled by the OFFSET1 and OFFSET0 bits (default is off). The offset voltage reduces the total available input range 4% (3% for the 75 mV value) before the onset of clipped conversion results. To restore the full range of the ADC, calibrate the offset voltage by the digital offset calibration register (OFC[2:0]). See Offset and Full-Scale Calibration Registers and Calibration Commands (OFSCAL and GANCAL) sections for details.