JAJSHJ6B December   2011  – June 2019 AFE030

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ブロック図
  4. 4 改訂履歴
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Thermal Information
    4. 7.4  Electrical Characteristics: Transmitter (Tx), Tx_DAC
    5. 7.5  Electrical Characteristics: Transmitter (Tx), Tx_PGA
    6. 7.6  Electrical Characteristics: Transmitter (Tx), Tx_FILTER
    7. 7.7  Electrical Characteristics: Power Amplifier (PA)
    8. 7.8  Electrical Characteristics: Receiver (Rx), Rx PGA1
    9. 7.9  Electrical Characteristics: Receiver (Rx), Rx Filter
    10. 7.10 Electrical Characteristics: Receiver (Rx), Rx PGA2
    11. 7.11 Electrical Characteristics: Digital
    12. 7.12 Electrical Characteristics: Two-Wire Interface
    13. 7.13 Electrical Characteristics: Zero-Crossing Detector
    14. 7.14 Electrical Characteristics: Internal Bias Generator
    15. 7.15 Electrical Characteristics: Power Supply
    16. 7.16 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Requirements
    2. 8.2 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 PA Block
      2. 9.3.2 Tx Block
      3. 9.3.3 Rx Block
      4. 9.3.4 DAC Block
      5. 9.3.5 REF1 and REF2 Blocks
      6. 9.3.6 Zero Crossing Detector Block
      7. 9.3.7 ETx and ERx Blocks
    4. 9.4 Power Supplies
    5. 9.5 Pin Descriptions
      1. 9.5.1 Current Overload
      2. 9.5.2 Thermal Overload
    6. 9.6 Calibration Modes
      1. 9.6.1 Tx Calibration Mode
      2. 9.6.2 Rx Calibration Mode
    7. 9.7 Serial Interface
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
    3. 10.3 Line-Coupling Circuit
    4. 10.4 Circuit Protection
    5. 10.5 Thermal Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 TINA-TI™ (無料のダウンロード・ソフトウェア)
        2. 11.1.1.2 TI Precision Designs
        3. 11.1.1.3 WEBENCH Filter Designer
      2. 11.1.2 電力線通信開発者用キット
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.4 DAC Block

The DAC block consists only of the 10-bit DAC. The use of the DAC is recommended for best performance. The serial interface is used to write directly to the DAC registers when the DAC pin (pin 7) is driven high. Placing the DAC pin into a high state configures the SPI for direct serial interface to the DAC. Use the following sequence to write to the DAC:

  • Set CS low.
  • Set the DAC pin (pin 7) high.
  • Write a 10-bit word to DIN. The DAC register is left-justified and truncates more than 10 bits.
  • CS high updates the DAC.

Refer to Figure 35 for an illustration of this sequence.

AFE030 tim_dac_boa130.gifFigure 35. Writing to the DAC Register

Table 7 lists the DAC Register configurations.

Table 7. DAC Registers

DAC PIN HIGH:
DAC REGISTER <15:0>		 LOCATION
(0 = LSB)		 DEFAULT R/W FUNCTION
BIT NAME
DAC<0> 0 — W Truncated
DAC<1> 1 — W Truncated
DAC<2> 2 — W Truncated
DAC<3> 3 — W Truncated
DAC<4> 4 — W Truncated
DAC<5> 5 — W Truncated
DAC<6> 6 — W DAC bit 0 = DAC LSB
DAC<7> 7 — W DAC bit 1
DAC<8> 8 — W DAC bit 2
DAC<9> 9 — W DAC bit 3
DAC<10> 10 — W DAC bit 4
DAC<11> 11 — W DAC bit 5
DAC<12> 12 — W DAC bit 6
DAC<13> 13 — W DAC bit 7
DAC<14> 14 — W DAC bit 8
DAC<15> 15 — W DAC bit 9 = DAC MSB