JAJSS68 November 2023 AM625SIP
ADVANCE INFORMATION
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
This section describes the device power sequence requirements for the VDDS_MEM_1P1 and VDDS_MEM_1P8 power rails relative to the other device power rails, which have been defined in the Power-Up Sequencing and Power-Down Sequencing sections of the AM62x Sitara Processors Datasheet.
The VDDS_MEM_1P1 power rail should be sourced from the same power supply that is sourcing VDDS_DDR. Therefore, the VDDS_MEM_1P1 power rail should ramp up and down with the power rails associated with waveform E.
The VDDS_MEM_1P8 power rail should ramp up and down with the power rails associated with waveform C.
For additional power sequence requirement details associated with the integrated LPDDR4 SDRAM, see the Integrated Silicon Solution (ISSI®) IS43/46LQ16256B Datasheet .