JAJSQZ4B データシート

JAJSQZ4B March 2023 – September 2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1

PRODUCTION DATA

1
1 特長
2 アプリケーション
3 概要
1. 3.1 機能ブロック図
4 Device Comparison
1. 4.1 Related Products
5 Terminal Configuration and Functions
1. 5.1 Pin Diagrams
2. 5.2 Pin Attributes
  1. 11
  2. 12
3. 5.3 Signal Descriptions
  1. 14
  2. 5.3.1 CPSW3G
    1. 5.3.1.1 MAIN Domain
      1. 17
      2. 18
      3. 19
      4. 20
  3. 5.3.2 CPTS
    1. 5.3.2.1 MAIN Domain
      1. 23
  4. 5.3.3 CSI-2
    1. 5.3.3.1 MAIN Domain
      1. 26
  5. 5.3.4 DDRSS
    1. 5.3.4.1 MAIN Domain
      1. 29
  6. 5.3.5 DSS
    1. 5.3.5.1 MAIN Domain
      1. 32
  7. 5.3.6 ECAP
    1. 5.3.6.1 MAIN Domain
      1. 35
      2. 36
      3. 37
  8. 5.3.7 Emulation and Debug
    1. 5.3.7.1 MAIN Domain
      1. 40
    2. 5.3.7.2 MCU Domain
      1. 42
  9. 5.3.8 EPWM
    1. 5.3.8.1 MAIN Domain
      1. 45
      2. 46
      3. 47
      4. 48
  10. 5.3.9 EQEP
    1. 5.3.9.1 MAIN Domain
      1. 51
      2. 52
      3. 53
  11. 5.3.10 GPIO
    1. 5.3.10.1 MAIN Domain
      1. 56
      2. 57
    2. 5.3.10.2 MCU Domain
      1. 59
  12. 5.3.11 GPMC
    1. 5.3.11.1 MAIN Domain
      1. 62
  13. 5.3.12 I2C
    1. 5.3.12.1 MAIN Domain
      1. 65
      2. 66
      3. 67
      4. 68
    2. 5.3.12.2 MCU Domain
      1. 70
    3. 5.3.12.3 WKUP Domain
      1. 72
  14. 5.3.13 MCAN
    1. 5.3.13.1 MAIN Domain
      1. 75
    2. 5.3.13.2 MCU Domain
      1. 77
      2. 78
  15. 5.3.14 MCASP
    1. 5.3.14.1 MAIN Domain
      1. 81
      2. 82
      3. 83
  16. 5.3.15 MCSPI
    1. 5.3.15.1 MAIN Domain
      1. 86
      2. 87
      3. 88
    2. 5.3.15.2 MCU Domain
      1. 90
      2. 91
  17. 5.3.16 MDIO
    1. 5.3.16.1 MAIN Domain
      1. 94
  18. 5.3.17 MMC
    1. 5.3.17.1 MAIN Domain
      1. 97
      2. 98
      3. 99
  19. 5.3.18 OSPI
    1. 5.3.18.1 MAIN Domain
      1. 102
  20. 5.3.19 Power Supply
    1. 104
  21. 5.3.20 Reserved
    1. 106
  22. 5.3.21 System and Miscellaneous
    1. 5.3.21.1 Boot Mode Configuration
      1. 5.3.21.1.1 MAIN Domain
        
        110
    2. 5.3.21.2 Clock
      1. 5.3.21.2.1 MCU Domain
        
        113
      2. 5.3.21.2.2 WKUP Domain
        
        115
    3. 5.3.21.3 System
      1. 5.3.21.3.1 MAIN Domain
        
        118
      2. 5.3.21.3.2 MCU Domain
        
        120
      3. 5.3.21.3.3 WKUP Domain
        
        122
    4. 5.3.21.4 VMON
      1. 124
  23. 5.3.22 TIMER
    1. 5.3.22.1 MAIN Domain
      1. 127
    2. 5.3.22.2 MCU Domain
      1. 129
    3. 5.3.22.3 WKUP Domain
      1. 131
  24. 5.3.23 UART
    1. 5.3.23.1 MAIN Domain
      1. 134
      2. 135
      3. 136
      4. 137
      5. 138
      6. 139
      7. 140
    2. 5.3.23.2 MCU Domain
      1. 142
    3. 5.3.23.3 WKUP Domain
      1. 144
  25. 5.3.24 USB
    1. 5.3.24.1 MAIN Domain
      1. 147
      2. 148
4. 5.4 Pin Connectivity Requirements
6 Specifications
7 Detailed Description
8 Applications, Implementation, and Layout
9 Device and Documentation Support
10Revision History
11Mechanical, Packaging, and Orderable Information
1. 11.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

AMB|484

サーマルパッド・メカニカル・データ

発注情報

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6.11.5.11.1 GPMC and NOR Flash — Synchronous Mode

Table 6-63 and Table 6-64 present timing requirements and switching characteristics for GPMC and NOR Flash - Synchronous Mode.

Table 6-63 GPMC and NOR Flash Timing Requirements — Synchronous Mode see Figure 6-46, Figure 6-47, and Figure 6-50

NO.	PARAMETER	DESCRIPTION	MODE⁽⁴⁾	MIN	MIN	UNIT
NO.	PARAMETER	DESCRIPTION	MODE⁽⁴⁾	GPMC_FCLK = 100 MHz⁽¹⁾	GPMC_FCLK = 133 MHz⁽¹⁾	UNIT
F12	t_su(dV-clkH)	Setup time, input data GPMC_AD[15:0] valid before output clock GPMC_CLK high	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	1.61	0.92	ns
F12	t_su(dV-clkH)		not_div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	0.86	3.41	ns
F13	t_h(clkH-dV)	Hold time, input data GPMC_AD[15:0] valid after output clock GPMC_CLK high	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	2.09	2.09	ns
F13	t_h(clkH-dV)		not_div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	2.09	2.09	ns
F21	t_{su(waitV-clkH)}	Setup time, input wait GPMC_WAIT[j]⁽²⁾⁽³⁾ valid before output clock GPMC_CLK high	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	1.61	0.92	ns
F21	t_{su(waitV-clkH)}		not_div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	0.86	3.41	ns
F22	t_{h(clkH-waitV)}	Hold time, input wait GPMC_WAIT[j]⁽²⁾⁽³⁾ valid after output clock GPMC_CLK high	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	2.09	2.09	ns
F22	t_{h(clkH-waitV)}		not_div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	2.09	2.09	ns

(1) GPMC_FCLK select

gpmc_fclk_sel[1:0] = 2b01 to select the 100MHz GPMC_FCLK
gpmc_fclk_sel[1:0] = 2b00 to select the 133MHz GPMC_FCLK

(2) In GPMC_WAIT[j], j is equal to 0 or 1.

(3) Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see General-Purpose Memory Controller (GPMC) section in the device TRM.

(4) For div_by_1_mode:

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
- GPMC_CLK frequency = GPMC_FCLK frequency

For not_div_by_1_mode:

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:
- GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4)

For GPMC_FCLK_MUX:

CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz

For TIMEPARAGRANULARITY_X1:

GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS)

Table 6-64 GPMC and NOR Flash Switching Characteristics – Synchronous Mode see Figure 6-46, Figure 6-47, Figure 6-48, Figure 6-49, and Figure 6-50

NO.⁽²⁾	PARAMETER	DESCRIPTION	MODE⁽¹⁶⁾	MIN	MAX	MIN	MAX	UNIT
NO.⁽²⁾	PARAMETER	DESCRIPTION	MODE⁽¹⁶⁾	100 MHz		133 MHz		UNIT
F0	1 / tc(clk)	Period, output clock GPMC_CLK⁽¹⁵⁾	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	10.00		7.52		ns
F1	t_w(clkH)	Typical pulse duration, output clock GPMC_CLK high	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	0.475P - 0.3⁽¹⁴⁾		0.475P - 0.3⁽¹⁴⁾		ns
F1	t_w(clkL)	Typical pulse duration, output clock GPMC_CLK low	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	0.475P - 0.3⁽¹⁴⁾		0.475P - 0.3⁽¹⁴⁾		ns
F2	t_d(clkH-csnV)	Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[i] transition⁽¹³⁾	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1; no extra_delay	F - 2.2 ⁽⁵⁾	F + 3.75	F - 2.2 ⁽⁵⁾	F + 3.75	ns
F3	t_{d(clkH-CSn[i]V)}	Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[i] invalid⁽¹³⁾	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1; no extra_delay	E - 2.2 ⁽⁴⁾	E + 3.18	E - 2.2 ⁽⁴⁾	E + 4.5	ns
F4	t_d(aV-clk)	Delay time, output address GPMC_A[27:1] valid to output clock GPMC_CLK first edge	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	B - 2.3 ⁽²⁾	B + 4.5	B - 2.3 ⁽²⁾	B + 4.5	ns
F5	t_d(clkH-aIV)	Delay time, output clock GPMC_CLK rising edge to output address GPMC_A[27:1] invalid	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	-2.3	4.5	-2.3	4.5	ns
F6	t_{d(be[x]nV-clk)}	Delay time, output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n valid to output clock GPMC_CLK first edge	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	B - 2.3 ⁽²⁾	B + 1.9	B - 2.3 ⁽²⁾	B + 1.9	ns
F7	t_{d(clkH-be[x]nIV)}	Delay time, output clock GPMC_CLK rising edge to output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n invalid⁽¹⁰⁾	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	D - 2.3⁽³⁾	D + 1.9	D - 2.3 ⁽³⁾	D + 1.9	ns
F7	t_{d(clkL-be[x]nIV)}	Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid⁽¹¹⁾	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	D - 2.3 ⁽³⁾	D + 1.9	D - 2.3 ⁽³⁾	D + 1.9	ns
F7	t_{d(clkL-be[x]nIV).}	Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid⁽¹²⁾	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	D - 2.3 ⁽³⁾	D + 1.9	D - 2.3 ⁽³⁾	D + 1.9	ns
F8	t_d(clkH-advn)	Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE transition	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1; no extra_delay	G - 2.3⁽⁶⁾	G + 4.5	G - 2.3 ⁽⁶⁾	G + 4.5	ns
F9	t_{d(clkH-advnIV)}	Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE invalid	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1; no extra_delay	D - 2.3 ⁽³⁾	D + 4.5	D - 2.3 ⁽³⁾	D + 4.5	ns
F10	t_d(clkH-oen)	Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn transition	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1; no extra_delay	H - 2.3 ⁽⁷⁾	H + 3.5	H - 2.3 ⁽⁷⁾	H + 3.5	ns
F11	t_{d(clkH-oenIV)}	Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn invalid	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1; no extra_delay	H - 2.3 ⁽⁷⁾	H + 3.5	H - 2.3 ⁽⁷⁾	H + 3.5	ns
F14	t_d(clkH-wen)	Delay time, output clock GPMC_CLK rising edge to output write enable GPMC_WEn transition	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1; no extra_delay	I - 2.3 ⁽⁸⁾	I + 4.5	I - 2.3 ⁽⁸⁾	I + 4.5	ns
F15	t_d(clkH-do)	Delay time, output clock GPMC_CLK rising edge to output data GPMC_AD[15:0] transition⁽¹⁰⁾	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	J - 2.3 ⁽⁹⁾	J + 2.7	J - 2.3 ⁽⁹⁾	J + 2.7	ns
F15	t_d(clkL-do)	Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition⁽¹¹⁾	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	J - 2.3 ⁽⁹⁾	J + 2.7	J - 2.3 ⁽⁹⁾	J + 2.7	ns
F15	t_d(clkL-do).	Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition⁽¹²⁾	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	J - 2.3 ⁽⁹⁾	J + 2.7	J - 2.3 ⁽⁹⁾	J + 2.7	ns
F17	t_{d(clkH-be[x]n)}	Delay time, output clock GPMC_CLK rising edge to output lower byte enable and command latch enable GPMC_BE0n_CLE transition⁽¹⁰⁾	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	J - 2.3 ⁽⁹⁾	J + 1.9	J - 2.3 ⁽⁹⁾	J + 1.9	ns
F17	t_{d(clkL-be[x]n)}	Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition⁽¹¹⁾	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	J - 2.3 ⁽⁹⁾	J + 1.9	J - 2.3 ⁽⁹⁾	J + 1.9	ns
F17	t_{d(clkL-be[x]n).}	Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition⁽¹²⁾	div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1	J - 2.3 ⁽⁹⁾	J + 1.9	J - 2.3 ⁽⁹⁾	J + 1.9	ns
F18	t_w(csnV)	Pulse duration, output chip select GPMC_CSn[i]⁽¹³⁾ low	Read	A		A		ns
F18	t_w(csnV)	Pulse duration, output chip select GPMC_CSn[i]⁽¹³⁾ low	Write	A		A		ns
F19	t_w(be[x]nV)	Pulse duration, output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n low	Read	C		C		ns
F19	t_w(be[x]nV)		Write	C		C		ns
F20	t_w(advnV)	Pulse duration, output address valid and address latch enable GPMC_ADVn_ALE low	Read	K		K		ns
F20	t_w(advnV)		Write	K		K		ns

(2) B = ClkActivationTime × GPMC_FCLK⁽¹⁴⁾

(3) For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾

(4) For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾

(5) For csn falling edge (CS activated):

Case GPMCFCLKDIVIDER = 0:
- F = 0.5 × CSExtraDelay × GPMC_FCLK⁽¹⁴⁾
Case GPMCFCLKDIVIDER = 1:
- F = 0.5 × CSExtraDelay × GPMC_FCLK⁽¹⁴⁾ if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even)
- F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK⁽¹⁴⁾ otherwise
Case GPMCFCLKDIVIDER = 2:
- F = 0.5 × CSExtraDelay × GPMC_FCLK⁽¹⁴⁾ if ((CSOnTime - ClkActivationTime) is a multiple of 3)
- F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK⁽¹⁴⁾ if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)
- F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK⁽¹⁴⁾ if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)

(6) For ADV falling edge (ADV activated):

Case GPMCFCLKDIVIDER = 0:
- G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁴⁾
Case GPMCFCLKDIVIDER = 1:
- G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁴⁾ if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are even)
- G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁴⁾ otherwise
Case GPMCFCLKDIVIDER = 2:
- G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁴⁾ if ((ADVOnTime - ClkActivationTime) is a multiple of 3)
- G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁴⁾ if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)
- G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁴⁾ if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Reading mode:

Case GPMCFCLKDIVIDER = 0:
- G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁴⁾
Case GPMCFCLKDIVIDER = 1:
- G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁴⁾ if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime are even)
- G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁴⁾ otherwise
Case GPMCFCLKDIVIDER = 2:
- G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁴⁾ if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)
- G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁴⁾ if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)
- G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁴⁾ if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Writing mode:

Case GPMCFCLKDIVIDER = 0:
- G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁴⁾
Case GPMCFCLKDIVIDER = 1:
- G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁴⁾ if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime are even)
- G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁴⁾ otherwise
Case GPMCFCLKDIVIDER = 2:
- G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁴⁾ if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)
- G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁴⁾ if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)
- G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁴⁾ if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)

(7) For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):

Case GPMCFCLKDIVIDER = 0:
- H = 0.5 × OEExtraDelay × GPMC_FCLK⁽¹⁴⁾
Case GPMCFCLKDIVIDER = 1:
- H = 0.5 × OEExtraDelay × GPMC_FCLK⁽¹⁴⁾ if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are even)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK⁽¹⁴⁾ otherwise
Case GPMCFCLKDIVIDER = 2:
- H = 0.5 × OEExtraDelay × GPMC_FCLK⁽¹⁴⁾ if ((OEOnTime - ClkActivationTime) is a multiple of 3)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK⁽¹⁴⁾ if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)
- H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK⁽¹⁴⁾ if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)

For OE rising edge (OE deactivated):

Case GPMCFCLKDIVIDER = 0:
- H = 0.5 × OEExtraDelay × GPMC_FCLK⁽¹⁴⁾
Case GPMCFCLKDIVIDER = 1:
- H = 0.5 × OEExtraDelay × GPMC_FCLK⁽¹⁴⁾ if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are even)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK⁽¹⁴⁾ otherwise
Case GPMCFCLKDIVIDER = 2:
- H = 0.5 × OEExtraDelay × GPMC_FCLK⁽¹⁴⁾ if ((OEOffTime - ClkActivationTime) is a multiple of 3)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK⁽¹⁴⁾ if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)
- H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK⁽¹⁴⁾ if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)

(8) For WE falling edge (WE activated):

Case GPMCFCLKDIVIDER = 0:
- I = 0.5 × WEExtraDelay × GPMC_FCLK⁽¹⁴⁾
Case GPMCFCLKDIVIDER = 1:
- I = 0.5 × WEExtraDelay × GPMC_FCLK⁽¹⁴⁾ if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are even)
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁴⁾ otherwise
Case GPMCFCLKDIVIDER = 2:
- I = 0.5 × WEExtraDelay × GPMC_FCLK⁽¹⁴⁾ if ((WEOnTime - ClkActivationTime) is a multiple of 3)
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁴⁾ if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)
- I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁴⁾ if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)

For WE rising edge (WE deactivated):

Case GPMCFCLKDIVIDER = 0:
- I = 0.5 × WEExtraDelay × GPMC_FCLK ⁽¹⁴⁾
Case GPMCFCLKDIVIDER = 1:
- I = 0.5 × WEExtraDelay × GPMC_FCLK⁽¹⁴⁾ if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are even)
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁴⁾ otherwise
Case GPMCFCLKDIVIDER = 2:
- I = 0.5 × WEExtraDelay × GPMC_FCLK⁽¹⁴⁾ if ((WEOffTime - ClkActivationTime) is a multiple of 3)
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁴⁾ if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)
- I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁴⁾ if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)

(9) J = GPMC_FCLK⁽¹⁴⁾

(10) First transfer only for CLK DIV 1 mode.

(11) Half cycle; for all data after initial transfer for CLK DIV 1 mode.

(12) Half cycle of GPMC_CLKOUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLKOUT divide down from GPMC_FCLK.

(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.

(14) P = GPMC_CLK period in ns

(15) Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the GPMC_CONFIG1_i configuration register bit field GPMCFCLKDIVIDER.

(16) For div_by_1_mode:

GPMC_CONFIG1_i register: GPMCFCLKDIVIDER = 0h:
- GPMC_CLK frequency = GPMC_FCLK frequency

For GPMC_FCLK_MUX:

CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz

For TIMEPARAGRANULARITY_X1:

GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS)

For no extra_delay:

GPMC_CONFIG2_i Register: CSEXTRADELAY = 0h = CSn Timing control signal is not delayed
GPMC_CONFIG4_i Register: WEEXTRADELAY = 0h = nWE timing control signal is not delayed
GPMC_CONFIG4_i Register: OEEXTRADELAY = 0h = nOE timing control signal is not delayed
GPMC_CONFIG3_i Register: ADVEXTRADELAY = 0h = nADV timing control signal is not delayed