JAJSU42A April   2022  – April 2024 BQ76922

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information BQ76922
    5. 6.5  Supply Current
    6. 6.6  Digital I/O
    7. 6.7  LD Pin
    8. 6.8  Precharge (PCHG) and Predischarge (PDSG) FET Drive
    9. 6.9  FUSE Pin Functionality
    10. 6.10 REG18 LDO
    11. 6.11 REG0 Pre-regulator
    12. 6.12 REG1 LDO
    13. 6.13 Voltage References
    14. 6.14 Coulomb Counter
    15. 6.15 Coulomb Counter Digital Filter (CC1)
    16. 6.16 Current Measurement Digital Filter (CC2)
    17. 6.17 Current Wake Detector
    18. 6.18 Analog-to-Digital Converter
    19. 6.19 Cell Balancing
    20. 6.20 Cell Open Wire Detector
    21. 6.21 Internal Temperature Sensor
    22. 6.22 Thermistor Measurement
    23. 6.23 Internal Oscillators
    24. 6.24 High-side NFET Drivers
    25. 6.25 Comparator-Based Protection Subsystem
    26. 6.26 Timing Requirements – I2C Interface, 100kHz Mode
    27. 6.27 Timing Requirements – I2C Interface, 400kHz Mode
    28. 6.28 Timing Requirements – HDQ Interface
    29. 6.29 Interface Timing Diagrams
    30. 6.30 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Diagnostics
    4. 7.4  Device Configuration
      1. 7.4.1 Commands and Subcommands
      2. 7.4.2 Configuration Using OTP or Registers
      3. 7.4.3 Device Security
      4. 7.4.4 Scratchpad Memory
    5. 7.5  Measurement Subsystem
      1. 7.5.1  Voltage Measurement
        1. 7.5.1.1 Voltage Measurement Schedule
        2. 7.5.1.2 Using VC Pins for Cells Versus Interconnect
        3. 7.5.1.3 Cell 1 Voltage Validation During SLEEP Mode
      2. 7.5.2  General Purpose ADCIN Functionality
      3. 7.5.3  Coulomb Counter and Digital Filters
      4. 7.5.4  Synchronized Voltage and Current Measurement
      5. 7.5.5  Internal Temperature Measurement
      6. 7.5.6  Thermistor Temperature Measurement
      7. 7.5.7  Factory Trim of Voltage ADC
      8. 7.5.8  Voltage Calibration (ADC Measurements)
      9. 7.5.9  Voltage Calibration (COV and CUV Protections)
      10. 7.5.10 Current Calibration
      11. 7.5.11 Temperature Calibration
    6. 7.6  Primary and Secondary Protection Subsystems
      1. 7.6.1 Protections Overview
      2. 7.6.2 Primary Protections
      3. 7.6.3 Secondary Protections
      4. 7.6.4 High-Side NFET Drivers
      5. 7.6.5 Protection FETs Configuration and Control
        1. 7.6.5.1 FET Configuration
        2. 7.6.5.2 PRECHARGE and PREDISCHARGE Modes
      6. 7.6.6 Load Detect Functionality
    7. 7.7  Device Hardware Features
      1. 7.7.1  Voltage References
      2. 7.7.2  ADC Multiplexer
      3. 7.7.3  LDOs
        1. 7.7.3.1 Preregulator Control
        2. 7.7.3.2 REG1 LDO Control
      4. 7.7.4  Standalone Versus Host Interface
      5. 7.7.5  Multifunction Pin Controls
      6. 7.7.6  RST_SHUT Pin Operation
      7. 7.7.7  CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
      8. 7.7.8  ALERT Pin Operation
      9. 7.7.9  Fuse Drive
      10. 7.7.10 Cell Open Wire
      11. 7.7.11 Low Frequency Oscillator
      12. 7.7.12 High Frequency Oscillator
    8. 7.8  Device Functional Modes
      1. 7.8.1 Overview
      2. 7.8.2 NORMAL Mode
      3. 7.8.3 SLEEP Mode
      4. 7.8.4 DEEPSLEEP Mode
      5. 7.8.5 SHUTDOWN Mode
      6. 7.8.6 CONFIG_UPDATE Mode
    9. 7.9  Serial Communications Interface
      1. 7.9.1 Serial Communications Overview
      2. 7.9.2 I2C Communications
      3. 7.9.3 HDQ Communications
    10. 7.10 Cell Balancing
      1. 7.10.1 Cell Balancing Overview
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements (Example)
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plot
      4. 8.2.4 Calibration Process
    3. 8.3 Random Cell Connection Support
    4. 8.4 Startup Timing
    5. 8.5 FET Driver Turn-Off
    6. 8.6 Unused Pins
  10. 9 Power Supply Requirements
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 サード・パーティ製品に関する免責事項
    2. 11.2 Documentation Support
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RSN|32
サーマルパッド・メカニカル・データ
発注情報

8.2.2 Detailed Design Procedure

  • Determine the number of series cells.
    • This value depends on the cell chemistry and the load requirements of the system. For example, to support a minimum battery voltage of 12.5V using Li-CO2 type cells with a cell minimum voltage of 2.5V, there needs to be at least 5-series cells.
    • For the correct cell connections, see Section 7.5.1.2.
  • Protection FET selection and configuration
    • The BQ76922 device is designed for use with high-side NFET protection
    • The configuration should be selected for series versus parallel FETs, which may lead to different FET selection for charge versus discharge direction.
    • These FETs should be rated for the maximum:
      • Voltage, which should be approximately 5V (DC) to 10V (peak) per series cell.
      • Current, which should be calculated based on both the maximum DC current and the maximum transient current with some margin.
      • Power dissipation, which can be a factor of the RDS(ON) rating of the FET, the FET package, and the PCB design.
    • The overdrive level of the BQ76922 device charge pump should be selected based on RDS(ON) requirements for the protection FETs and their voltage handling requirements. If the FETs are selected with a maximum gate-to-source voltage of 15V, then the 11V overdrive mode within the BQ76922 device can be used. If the FETs are not specified to withstand this level, or there is a concern over gate leakage current on the FETs, the lower overdrive level of 5.5V can be selected.
  • Sense resistor selection
    • The resistance value should be selected to maximize the input range of the coulomb counter but not exceed the absolute maximum ratings, and avoid excessive heat generation within the resistor.
      • Using the normal maximum charge or discharge current, the sense resistor = 200mV / 20.0A = 10 mΩ maximum.
      • However, considering a short circuit discharge current of 80 A, the recommended maximum SRP, SRN voltage of approximately 0.75V, and the maximum SCD threshold of 500mV, the sense resistor should be below 500mV / 80A= 6.25mΩ maximum.
    • Further tolerance analysis (value tolerance, temperature variation, and so on) and PCB design margin should also be considered, so a sense resistor of 1mΩ is suitable with a 50ppm temperature coefficient and power rating of 1W.
  • The REG1 is selected to provide the supply for an external host processor, with output voltage selected for 3.3V.
    • The NPN BJT used for the REG0 preregulator should be selected to support the maximum collector-to-emitter voltage of the maximum charging voltage of 22V. The gain of the BJT should be chosen so it can provide the required maximum output current with a base current level that can be provided from the BQ76922 device.
    • The BJT should support the maximum current expected from the REG1 (maximum of 45mA, with short circuit current limit of up to approximately 80mA).
    • A diode can optionally be included in the collector circuit of the BJT, in order to avoid reverse current flow from BREG through the base-collector junction of the BJT to PACK+ during a pack short circuit event. This diode can be seen in Figure 8-2 at D2.
    • A large resistor (such as 10mΩ) is recommended from BREG to VSS, to avoid any unintended leakage current that may occur during SHUTDOWN mode.