JAJSSC1 November   2023 CC1312PSIP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 機能ブロック図
  6. 5 Revision History
  7. 6 Device Comparison
  8. 7 Pin Configuration and Functions
    1. 7.1 Pin Diagram – MOT Package (Top View)
    2. 7.2 Signal Descriptions – MOT Package
    3. 7.3 Connections for Unused Pins and Modules
  9. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Power Supply and Modules
    5. 8.5  Power Consumption - Power Modes
    6. 8.6  Power Consumption - Radio Modes
    7. 8.7  Nonvolatile (Flash) Memory Characteristics
    8. 8.8  Thermal Resistance Characteristics
    9. 8.9  RF Frequency Bands
    10. 8.10 861 MHz to 1054 MHz - Receive (RX)
    11. 8.11 861 MHz to 1054 MHz - Transmit (TX) 
    12. 8.12 861 MHz to 1054 MHz - PLL Phase Noise Wideband Mode
    13. 8.13 861 MHz to 1054 MHz - PLL Phase Noise Narrowband Mode
    14. 8.14 Timing and Switching Characteristics
      1. 8.14.1 Reset Timing
      2. 8.14.2 Wakeup Timing
      3. 8.14.3 Clock Specifications
        1. 8.14.3.1 48 MHz Crystal Oscillator (XOSC_HF) and RF frequency accuracy
        2. 8.14.3.2 48 MHz RC Oscillator (RCOSC_HF)
        3. 8.14.3.3 2 MHz RC Oscillator (RCOSC_MF)
        4. 8.14.3.4 32.768 kHz Crystal Oscillator (XOSC_LF) and RTC accuracy
        5. 8.14.3.5 32 kHz RC Oscillator (RCOSC_LF)
      4. 8.14.4 Synchronous Serial Interface (SSI) Characteristics
        1.       36
          1. 8.14.4.1.1 Synchronous Serial Interface (SSI) Characteristics
      5. 8.14.5 UART
        1. 8.14.5.1 UART Characteristics
    15. 8.15 Peripheral Characteristics
      1. 8.15.1 ADC
        1. 8.15.1.1 Analog-to-Digital Converter (ADC) Characteristics
      2. 8.15.2 DAC
        1. 8.15.2.1 Digital-to-Analog Converter (DAC) Characteristics
      3. 8.15.3 Temperature and Battery Monitor
        1. 8.15.3.1 Temperature Sensor
        2. 8.15.3.2 Battery Monitor
      4. 8.15.4 Comparators
        1. 8.15.4.1 Low-Power Clocked Comparator
        2. 8.15.4.2 Continuous Time Comparator
      5. 8.15.5 Current Source
        1. 8.15.5.1 Programmable Current Source
      6. 8.15.6 GPIO
        1. 8.15.6.1 GPIO DC Characteristics
    16. 8.16 Typical Characteristics
      1. 8.16.1 MCU Current
      2. 8.16.2 RX Current
      3. 8.16.3 TX Current
      4. 8.16.4 RX Performance
      5. 8.16.5 TX Performance
      6. 8.16.6 ADC Performance
      7. 8.16.7 Temperature Compensation
  10. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  System CPU
    3. 9.3  Radio (RF Core)
      1. 9.3.1 Proprietary Radio Formats
    4. 9.4  Memory
    5. 9.5  Sensor Controller
    6. 9.6  Cryptography
    7. 9.7  Timers
    8. 9.8  Serial Peripherals and I/O
    9. 9.9  Battery and Temperature Monitor
    10. 9.10 µDMA
    11. 9.11 Debug
    12. 9.12 Power Management
    13. 9.13 Clock Systems, production calibration and temperature compensation
    14. 9.14 Network Processor
    15. 9.15 Device Certification and Qualification
      1. 9.15.1 FCC Certification and Statement
      2. 9.15.2 IC/ISED Certification and Statement
    16. 9.16 Module Markings
    17. 9.17 End Product Labeling
    18. 9.18 Manual Information to the End User
  11. 10Application, Implementation, and Layout
    1. 10.1 Application Information
      1. 10.1.1 Typical Application Circuit
    2. 10.2 Device Connection and Layout Fundamentals
      1. 10.2.1 Reset
      2. 10.2.2 Unused Pins
    3. 10.3 PCB Layout Guidelines
      1. 10.3.1 General Layout Recommendations
      2. 10.3.2 RF Layout Recommendations
        1. 10.3.2.1 Antenna Placement and Routing
        2. 10.3.2.2 Transmission Line Considerations
    4. 10.4 Reference Designs
  12. 11Environmental Requirements and SMT Specifications
    1. 11.1 PCB Bending
    2. 11.2 Handling Environment
      1. 11.2.1 Terminals
      2. 11.2.2 Falling
    3. 11.3 Storage Condition
      1. 11.3.1 Moisture Barrier Bag Before Opened
      2. 11.3.2 Moisture Barrier Bag Open
    4. 11.4 PCB Assembly Guide
      1. 11.4.1 PCB Land Pattern & Thermal Vias
      2. 11.4.2 SMT Assembly Recommendations
      3. 11.4.3 PCB Surface Finish Requirements
      4. 11.4.4 Solder Stencil
      5. 11.4.5 Package Placement
      6. 11.4.6 Solder Joint Inspection
      7. 11.4.7 Rework and Replacement
      8. 11.4.8 Solder Joint Voiding
    5. 11.5 Baking Conditions
    6. 11.6 Soldering and Reflow Condition
  13. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
      1. 12.2.1 SimpleLink™ Microcontroller Platform
    3. 12.3 Documentation Support
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.15.2.1 Digital-to-Analog Converter (DAC) Characteristics

Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
General Parameters
Resolution 8 Bits
VDDS Supply voltage Any load, any VREF, pre-charge OFF, DAC charge-pump ON 1.8 3.8 V
External Load(4), any VREF, pre-charge OFF, DAC charge-pump OFF 2.0 3.8
Any load, VREF = DCOUPL, pre-charge ON 2.6 3.8
FDAC Clock frequency Buffer ON (recommended for external load) 16 250 kHz
Buffer OFF (internal load) 16 1000
Voltage output settling time VREF = VDDS, buffer OFF, internal load 13 1 / FDAC
VREF = VDDS, buffer ON, external capacitive load = 20 pF(3) 13.8
External capacitive load 20 200 pF
External resistive load 10 MΩ
Short circuit current 400 µA
ZMAX Max output impedance Vref = VDDS, buffer ON, CLK 250 kHz VDDS = 3.8 V, DAC charge-pump OFF 50.8 kΩ
VDDS = 3.0 V, DAC charge-pump ON 51.7
VDDS = 3.0 V, DAC charge-pump OFF 53.2
VDDS = 2.0 V, DAC charge-pump ON 48.7
VDDS = 2.0 V, DAC charge-pump OFF 70.2
VDDS = 1.8 V, DAC charge-pump ON 46.3
VDDS = 1.8 V, DAC charge-pump OFF 88.9
Internal Load - Continuous Time Comparator / Low Power Clocked Comparator
DNL Differential nonlinearity VREF = VDDS,
load = Continuous Time Comparator or Low Power Clocked Comparator
FDAC = 250 kHz		 ±1 LSB(1)
Differential nonlinearity VREF = VDDS,
load = Continuous Time Comparator or Low Power Clocked Comparator
FDAC = 16 kHz		 ±1.2
Offset error(2)
Load = Continuous Time Comparator		 VREF = VDDS = 3.8 V ±0.64 LSB(1)
VREF = VDDS = 3.0 V ±0.81
VREF = VDDS = 1.8 V ±1.27
VREF = DCOUPL, pre-charge ON ±3.43
VREF = DCOUPL, pre-charge OFF ±2.88
VREF = ADCREF ±2.37
Offset error(2)
Load = Low Power Clocked Comparator		 VREF = VDDS = 3.8 V ±0.78 LSB(1)
VREF = VDDS = 3.0 V ±0.77
VREF = VDDS = 1.8 V ±3.46
VREF = DCOUPL, pre-charge ON ±3.44
VREF = DCOUPL, pre-charge OFF ±4.70
VREF = ADCREF ±4.11
Max code output voltage variation(2)
Load = Continuous Time Comparator		 VREF = VDDS = 3.8 V ±1.53 LSB(1)
VREF = VDDS = 3.0 V ±1.71
VREF = VDDS = 1.8 V ±2.10
VREF = DCOUPL, pre-charge ON ±6.00
VREF = DCOUPL, pre-charge OFF ±3.85
VREF = ADCREF ±5.84
Max code output voltage variation(2)
Load = Low Power Clocked Comparator		 VREF = VDDS = 3.8 V ±2.92 LSB(1)
VREF =VDDS = 3.0 V ±3.06
VREF = VDDS = 1.8 V ±3.91
VREF = DCOUPL, pre-charge ON ±7.84
VREF = DCOUPL, pre-charge OFF ±4.06
VREF = ADCREF ±6.94
Output voltage range(2)
Load = Continuous Time Comparator		 VREF = VDDS = 3.8 V, code 1 0.03 V
VREF = VDDS = 3.8 V, code 255 3.62
VREF = VDDS = 3.0 V, code 1 0.02
VREF = VDDS = 3.0 V, code 255 2.86
VREF = VDDS = 1.8 V, code 1 0.01
VREF = VDDS = 1.8 V, code 255 1.71
VREF = DCOUPL, pre-charge OFF, code 1 0.01
VREF = DCOUPL, pre-charge OFF, code 255 1.21
VREF = DCOUPL, pre-charge ON, code 1 1.27
VREF = DCOUPL, pre-charge ON, code 255 2.46
VREF = ADCREF, code 1 0.01
VREF = ADCREF, code 255 1.41
Output voltage range(2)
Load = Low Power Clocked Comparator		 VREF = VDDS = 3.8 V, code 1 0.03 V
VREF = VDDS = 3.8 V, code 255 3.61
VREF = VDDS = 3.0 V, code 1 0.02
VREF = VDDS = 3.0 V, code 255 2.85
VREF = VDDS = 1.8 V, code 1 0.01
VREF = VDDS = 1.8 V, code 255 1.71
VREF = DCOUPL, pre-charge OFF, code 1 0.01
VREF = DCOUPL, pre-charge OFF, code 255 1.21
VREF = DCOUPL, pre-charge ON, code 1 1.27
VREF = DCOUPL, pre-charge ON, code 255 2.46
VREF = ADCREF, code 1 0.01
VREF = ADCREF, code 255 1.41
External Load
INL Integral nonlinearity VREF = VDDS, FDAC = 250 kHz ±1 LSB(1)
VREF = DCOUPL, FDAC = 250 kHz ±2
VREF = ADCREF, FDAC = 250 kHz ±1
DNL Differential nonlinearity VREF = VDDS, FDAC = 250 kHz ±1 LSB(1)
Offset error VREF = VDDS = 3.8 V ±0.40 LSB(1)
VREF = VDDS = 3.0 V ±0.50
VREF = VDDS = 1.8 V ±0.75
VREF = DCOUPL, pre-charge ON ±1.55
VREF = DCOUPL, pre-charge OFF ±1.30
VREF = ADCREF ±1.10
Max code output voltage variation VREF = VDDS = 3.8 V ±1.00 LSB(1)
VREF = VDDS = 3.0 V ±1.00
VREF = VDDS = 1.8 V ±1.00
VREF = DCOUPL, pre-charge ON ±3.45
VREF = DCOUPL, pre-charge OFF ±2.10
VREF = ADCREF ±1.90
Output voltage range
Load = Low Power Clocked Comparator		 VREF = VDDS = 3.8 V, code 1 0.03 V
VREF = VDDS = 3.8 V, code 255 3.61
VREF = VDDS = 3.0 V, code 1 0.02
VREF = VDDS = 3.0 V, code 255 2.85
VREF = VDDS = 1.8 V, code 1 0.02
VREF = VDDS = 1.8 V, code 255 1.71
VREF = DCOUPL, pre-charge OFF, code 1 0.02
VREF = DCOUPL, pre-charge OFF, code 255 1.20
VREF = DCOUPL, pre-charge ON, code 1 1.27
VREF = DCOUPL, pre-charge ON, code 255 2.46
VREF = ADCREF, code 1 0.02
VREF = ADCREF, code 255 1.42
(1) 1 LSB (VREF 3.8 V/3.0 V/1.8 V/DCOUPL/ADCREF) = 14.10 mV/11.13 mV/6.68 mV/4.67 mV/5.48 mV
(2) Includes comparator offset
(3) A load > 20 pF will increases the settling time
(4) Keysight 34401A Multimeter