JAJSNM9C February   1998  – December 2021 CD54HC273 , CD54HCT273 , CD74HC273 , CD74HCT273

PRODUCTION DATA  

  1. 特長
  2. 説明
  3. Revision History
  4. Pin Configuration and Functions
  5. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Prerequisite for Switching Characteristics
    6. 5.6 Switching Characteristics
  6. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
  7. Parameter Measurement Information
  8. Power Supply Recommendations
  9. Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • J|20
サーマルパッド・メカニカル・データ
発注情報

Electrical Characteristics

PARAMETER TEST CONDITIONS(2) VCC (V) 25℃ –40℃ to 85℃ –55℃ to 125℃ UNIT
MIN TYP MAX MIN MAX MIN MAX
HC TYPES
VIH High level input voltage 2 1.5 1.5 1.5 V
4.5 3.15 3.15 3.15
6 4.2 4.2 4.2
VIL Low level input voltage 2 0.5 0.5 0.5 V
4.5 1.35 1.35 1.35
6 1.8 1.8 1.8
VOH

High level output voltage

CMOS loads

IOH = – 20 μA 2 1.9 1.9 1.9 V
IOH = – 20 μA 4.5 4.4 4.4 4.4
IOH = – 20 μA 6 5.9 5.9 5.9

High level output voltage

TTL loads

IOH = – 4 mA 4.5 3.98 3.84 3.7 V
IOH = – 5.2 mA 6 5.48 5.34 5.2
VOL

Low level output voltage

CMOS loads

IOL = 20 μA 2 0.1 0.1 0.1 V
IOL = 20 μA 4.5 0.1 - 0.1 - 0.1
IOL = 20 μA 6 0.1 0.1 0.1

Low level output voltage

TTL loads

IOL = 4 mA 4.5 0.26 0.33 0.4 V
IOL = 5.2 mA 6 0.26 0.33 0.4
II Input leakage current VI = VCC or GND 6 ±0.1 ±1 ±1 mA
ICC Quiescent device current VI = VCC or GND 6 8 80 160 mA
HCT TYPES
VIH High level input voltage 4.5 to 5.5 2 2 2 V
VIL Low level input voltage 4.5 to 5.5 0.8 0.8 0.8 V
VOH

High level output voltage

CMOS loads

IOH = – 20 μA 4.5 4.4 4.4 4.4 V

High level output voltage

TTL loads

IOH = – 4 mA 4.5 3.98 3.84 3.7
VOL

Low level output voltage

CMOS loads

IOL = 20 μA 4.5 0.1 0.1 0.1 V

Low level output voltage

TTL loads

IOL = 4 mA 4.5 0.26 0.33 0.4
II Input leakage current VI = VCC or GND 5.5 ±0.1 ±1 ±1 μA
ICC Quiescent device current VI = VCC or GND 5.5 8 80 160 μA
ΔICC(1) Additional quiescent device current per input pin CLR input held at VCC –2.1 4.5 to 5.5 100 540 675 735 μA
Data inputs held at VCC –2.1 4.5 to 5.5 100 144 180 196 μA
CLK inputs held at VCC –2.1 4.5 to 5.5 100 540 675 735 μA
For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8mA.
VI = VIH or VIL, unless otherwise noted.