7.6.1.1 OECR1 Register (Address = 0h) [reset = 78h]
OECR1 is shown in Table 11.
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The OECR1 register contains bits that enable or disable individual output clock channels [19:16]
Table 11. OECR1 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7 |
RESERVED |
R |
0h |
Reserved |
6 |
Output Enable, CK19 |
R/W |
1h |
This bit controls the output enable signal for output channel CK19_P/CK19_N.
0h = Output Disabled
1h = Output Enabled
|
5 |
Output Enable, CK18 |
R/W |
1h |
This bit controls the output enable signal for output channel CK18_P/CK18_N.
0h = Output Disabled
1h = Output Enabled
|
4 |
Output Enable, CK17 |
R/W |
1h |
This bit controls the output enable signal for output channel CK17_P/CK17_N.
0h = Output Disabled
1h = Output Enabled
|
3 |
Output Enable, CK16 |
R/W |
1h |
This bit controls the output enable signal for output channel CK16_P/CK16_N.
0h = Output Disabled
1h = Output Enabled
|
2-0 |
RESERVED |
R |
0h |
Reserved |