JAJSCZ1D January   2017  – February 2024 CDCE813-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Configuration
      2. 7.3.2 Default Device Configuration
      3. 7.3.3 I2C Serial Interface
      4. 7.3.4 Data Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA and SCL Hardware Interface
    5. 7.5 Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Spread-Spectrum Clock (SSC)
        2. 8.2.2.2 PLL Frequency Planning
        3. 8.2.2.3 Crystal Oscillator Start-Up
        4. 8.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 8.2.2.5 Unused Inputs and Outputs
        6. 8.2.2.6 Switching Between XO and VCXO Mode
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Register Maps
    1. 9.1 I2C Configuration Registers
  11. 10デバイスおよびドキュメントのサポート
    1. 10.1 ドキュメントのサポート
      1. 10.1.1 関連資料
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 商標
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

GUID-A077F401-4E59-401A-A670-EDF0BD87DA49-low.gif Figure 4-1 PW Package14-Pin TSSOPTop View
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
GND 5, 10 G Ground
SCL/S2 12 I SCL: serial clock input LVCMOS (default configuration), 500-kΩ internal pullup; or
S2: user-programmable control input, LVCMOS input, 500-kΩ internal pullup
SDA/S1 13 I/O or I SDA: bidirectional serial data input or output (default configuration), LVCMOS internal pullup; or
S1: user-programmable control input, LVCMOS input, 500-kΩ internal pullup
S0 2 I User-programmable control input S0, LVCMOS input, 500-kΩ internal pullup
CDCE813-Q1 default:
S0 = 1: Y1 is 3-state,
S0 = 0: Y1 is 3-state
CDCE813R02-Q1 default:
S0 = 1: Y1 is enabled,
S0 = 0: Y1 is 3-state
Vctr 4 I VCXO control voltage (leave open or pull up when not used)
VDD 3 P 1.8-V power supply for the device
VDDOUT 6, 7 P 3.3-V or 2.5-V supply for all outputs
Xin/CLK 1 I Crystal oscillator input or LVCMOS clock input (selectable through the I2C bus)
Xout 14 O Crystal oscillator output (leave open or pull up when not used)
Y1 11 O LVCMOS output
Y2 9 O LVCMOS output
Y3 8 O LVCMOS output
(1) G = Ground, I = Input, O = Output, P = Power