JAJSCZ1D January   2017  – February 2024 CDCE813-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Configuration
      2. 7.3.2 Default Device Configuration
      3. 7.3.3 I2C Serial Interface
      4. 7.3.4 Data Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA and SCL Hardware Interface
    5. 7.5 Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Spread-Spectrum Clock (SSC)
        2. 8.2.2.2 PLL Frequency Planning
        3. 8.2.2.3 Crystal Oscillator Start-Up
        4. 8.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 8.2.2.5 Unused Inputs and Outputs
        6. 8.2.2.6 Switching Between XO and VCXO Mode
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Register Maps
    1. 9.1 I2C Configuration Registers
  11. 10デバイスおよびドキュメントのサポート
    1. 10.1 ドキュメントのサポート
      1. 10.1.1 関連資料
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 商標
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.2 Default Device Configuration

The internal EEPROM of the CDCE813-Q1 device is pre-configured with a factory default configuration as shown in Figure 7-1 (the input frequency is routed through PLL1 to the outputs as a default). This mode can be used to clean the jitter of an incoming clock signal. For the CDCE813-Q1, the outputs are disabled by default and must be turned on through I2C. For the CDCE813R02-Q1, output Y1 is enabled through the S0 control pin (active high), while outputs Y2 and Y3 are either in a tri-state condition or disabled by the register default. Y1 is enabled when S0 is floating because S0 has an internal pullup.

The default setting appears either after power is supplied or after a power-down – power-up sequence until it is reprogrammed by the user to a different application configuration. A new register setting is programmed through the serial I2C interface.

GUID-F0A9A5D3-1ED9-4A4A-AC6D-580AA4CAAD78-low.gif Figure 7-1 CDCE813-Q1 Default Configuration
GUID-15DE920F-266D-4A85-9976-8EBA840B1436-low.gif Figure 7-2 CDCE813R02-Q1 Default Configuration

Table 7-6 shows the factory default setting for the Control Terminal Register.

Note:

Even though eight different register settings are possible, in the default configuration, only the first two settings (0 and 1) can be selected with S0, as S1 and S2 are configured as programming pins in default mode.

Table 7-6 Factory Default Setting for Control Terminal Register (1)
GPNEXTERNAL CONTROL PINSY1PLL1 SETTINGS
OUTPUT
SELECTION		FREQUENCY
SELECTION		SSC
SELECTION		OUTPUT
SELECTION
S2S1S0Y1FS1SSC1Y2Y3
CDCE813-Q1SCL (I2C)SDA (I2C)03-statefVCO1_0Off3-state
SCL (I2C)SDA (I2C)13-statefVCO1_0Off3-state
CDCE813R02-Q1SCL (I2C)SDA (I2C)03-statefVCO1_0Off3-state
SCL (I2C)SDA (I2C)1EnabledfVCO1_0Off3-state
(1) In default mode or when programmed respectively, S1 and S2 act as serial programming interface, I2C. They do not have any control-pin function but they are internally interpreted as if S1 = 0 and S2 = 0. For the CDCE813-Q1, S0 is an unused control pin by default. For the CDCE813R02-Q1, S0 provides output enable (OE) control output Y1 only.