JAJSDY3F July 2017 – January 2024 CDCI6214
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
There are no restrictions from the device for applying power to the supply pins. From an application perspective, TI recommends to either apply all VDDs at the same time or apply VDDREF first. The digital core is connected to VDDREF, and thus the settings of the EEPROM are applied automatically. All VDDs should reach 95% of final value within 2 ms. RESETN should be held low before VDDREF reaches 95% of the final value.
TI recommends adding a 4.7-kΩ pullup resistor on RESETN and a 470-nF capacitor to ground to provide additional delay in release of RESETN at power-up. When powering up the CDCI6214 from reset, the rise of the RESETN pin must be delayed to allow the voltage on the VDD pins to stabilize.
An unstable voltage on the VDD pin may cause an improper device startup with the rise of the RESETN pin, resulting in a PLL unlock. VDD instability may occur in cases where VDD is toggled repeatedly and does not ramp with appropriate settling time. The power supply must ramp and be stable within the time specified in the Timing Characteristics table. In the event of a PLL unlock at startup, recalibrate the PLL. Either setting the recal bit, R0[4], to a '1' or pulling the RESETN pin low then high will recalibrate the PLL.