JAJSDY3F July   2017  – January 2024 CDCI6214

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  EEPROM Characteristics
    6. 6.6  Reference Input, Single-Ended and Differential Mode Characteristics (REFP, REFN, FB_P, FB_N)
    7. 6.7  Reference Input, Crystal Mode Characteristics (XIN, XOUT)
    8. 6.8  General-Purpose Input and Output Characteristics (GPIO[4:1], SYNC/RESETN)
    9. 6.9  Triple Level Input Characteristics (EEPROMSEL, REFSEL)
    10. 6.10 Reference Mux Characteristics
    11. 6.11 Phase-Locked Loop Characteristics
    12. 6.12 Closed-Loop Output Jitter Characteristics
    13. 6.13 Output Mux Characteristics
    14. 6.14 LVCMOS Output Characteristics
    15. 6.15 HCSL Output Characteristics
    16. 6.16 LVDS DC-Coupled Output Characteristics
    17. 6.17 Programmable Differential AC-Coupled Output Characteristics
    18. 6.18 Output Skew and Delay Characteristics
    19. 6.19 Output Synchronization Characteristics
    20. 6.20 Timing Characteristics
    21. 6.21 I2C-Compatible Serial Interface Characteristics (SDA/GPIO2, SCL/GPIO3)
    22. 6.22 Timing Requirements, I2C-Compatible Serial Interface (SDA/GPIO2, SCL/GPIO3)
    23. 6.23 Power Supply Characteristics
    24. 6.24 Typical Characteristics
  8. Parameter Measurement Information
    1. 7.1 Parameters
      1. 7.1.1 Reference Inputs
      2. 7.1.2 Outputs
      3. 7.1.3 Serial Interface
      4. 7.1.4 Power Supply
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reference Block
        1. 8.3.1.1 Input Stages
          1. 8.3.1.1.1 Crystal Oscillator
          2. 8.3.1.1.2 LVCMOS
          3. 8.3.1.1.3 Differential AC-Coupled
        2. 8.3.1.2 Reference Mux
        3. 8.3.1.3 Reference Divider
          1. 8.3.1.3.1 Doubler
        4. 8.3.1.4 Bypass-Mux
        5. 8.3.1.5 Zero Delay, Internal and External Path
      2. 8.3.2 Phase-Locked Loop
      3. 8.3.3 Clock Distribution
        1. 8.3.3.1 Output Channel
        2. 8.3.3.2 Divider Glitch-Less Update
      4. 8.3.4 Control Pins
        1. 8.3.4.1 Global and Individual Output Enable: OE and OE_Y[4:1]
      5. 8.3.5 Operation Modes
      6. 8.3.6 Divider Synchronization - SYNC
      7. 8.3.7 EEPROM - Cyclic Redundancy Check
      8. 8.3.8 Power Supplies
        1. 8.3.8.1 Power Management
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Mode
      2. 8.4.2 Serial Interface Mode
        1. 8.4.2.1 Fall-Back Mode
    5. 8.5 Programming
      1. 8.5.1 Recommended Programming Procedure
      2. 8.5.2 EEPROM Access
      3. 8.5.3 Device Defaults
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
    4. 9.4 Initialization Setup
    5. 9.5 Power Supply Recommendations
      1. 9.5.1 Power-Up Sequence
      2. 9.5.2 De-Coupling
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Examples
  11. 10Register Maps
    1. 10.1 CDCI6214 Registers
    2. 10.2 EEPROM Map
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
      2. 11.1.2 Device Nomenclature
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • RGE|24
サーマルパッド・メカニカル・データ
発注情報

Detailed Design Procedure

For this application, TI recommends the following steps:

  1. Decide how the device shall receive the register settings to plan for in-system programming of the EEPROM.
  2. Choose which operation mode to use on the device (I2C or GPIOs) and which pins are inputs and which are outputs (see registers

    GENERIC0

    ,

    GENERIC1

    , and

    GENERIC2

    ).
  3. Consider that the serial interface and the GPIOs are supplied by VDDREF as well as the input pins (for example, a 3.3-V crystal oscillator (XO) driving XIN forces uses 3.3-V I2C).
  4. Keep track of which voltage levels the output supplies will have. There are configuration bits in the output channels (see CH1_CTRL5,

    CH2_CTRL5

    , CH3_CTRL5, and CH4_CTRL5).
  5. Consider which output frequency has the most stringent phase noise specifications. Select this frequency to decide on the reference and VCO frequency.
  6. Cross-check if your specific bandwidth requirement for an external reference can be achieved using the internal loop filter components (see registers PLL1 and PLL2).
  7. Optimize the clock distribution using output muxes to run the least amount of blocks to conserve power,
  8. For HCSL output buffer format, optimize the signal integrity and slew rate at the receiver input using a series resistor between device pin and the 50 Ω termination to GND.Y1,Y4 provide higher slew rates compared to Y2,Y3.

Use Equation 1 through Equation 4 to calculate the a basic frequency plan or use the provided software TICS Pro to generate settings.

Note:

The user has to ensure PLL stability is given by applying the adequate loop filter and charge pump settings. A phase margin of ≥ 68° is recommended. The target bandwidth is recommended between 600 kHz .. 1100 kHz.

Equation 1. fY0 = fXIN = fREF
Equation 2. fPFD = fREF / ip_ref_div

where

  • ip_ref_div ≥ 1
  • 1 MHz <= fPFD <= 100 MHz
Equation 3. fVCO = fPFD · pll_nc · (pll_ps + 4)

with

  • 2400 <= fVCO <= 2800
  • 0 <= pll_ps <= 2
Equation 4. fY[4:1] = fVCO / ((pll_ps[ab] + 4) · ch[4:1]_iod_div)

with

  • 0 <= pll_ps[ab] <= 2
  • 1 <= ch[4:1]_iod_div <= 16383
  • 44.1 kHz <= fY[4:1] <= 350 MHz

with

  • 1 <= IP_REF_DIV <= 255
  • IP_EN_DBLR = 0
  • 1 MHz <= fPFD <= 100 MHz

with

  • IP_REF_DIV = 0
  • IP_EN_DBLR = 1
  • 1 MHz <= fPFD <= 100 MHz

with

  • 2400 <= fVCO <= 2800
  • 0 <= PLL_PS_MODE <= 2

with

  • 0 <= PLL_PS[AB]_MODE <= 2
  • 1 <= CH[4:1]_IOD_DIV <= 16383
  • 44.1 kHz <= fY[4:1] <= 350 MHz