JAJSDY3F July   2017  – January 2024 CDCI6214

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  EEPROM Characteristics
    6. 6.6  Reference Input, Single-Ended and Differential Mode Characteristics (REFP, REFN, FB_P, FB_N)
    7. 6.7  Reference Input, Crystal Mode Characteristics (XIN, XOUT)
    8. 6.8  General-Purpose Input and Output Characteristics (GPIO[4:1], SYNC/RESETN)
    9. 6.9  Triple Level Input Characteristics (EEPROMSEL, REFSEL)
    10. 6.10 Reference Mux Characteristics
    11. 6.11 Phase-Locked Loop Characteristics
    12. 6.12 Closed-Loop Output Jitter Characteristics
    13. 6.13 Output Mux Characteristics
    14. 6.14 LVCMOS Output Characteristics
    15. 6.15 HCSL Output Characteristics
    16. 6.16 LVDS DC-Coupled Output Characteristics
    17. 6.17 Programmable Differential AC-Coupled Output Characteristics
    18. 6.18 Output Skew and Delay Characteristics
    19. 6.19 Output Synchronization Characteristics
    20. 6.20 Timing Characteristics
    21. 6.21 I2C-Compatible Serial Interface Characteristics (SDA/GPIO2, SCL/GPIO3)
    22. 6.22 Timing Requirements, I2C-Compatible Serial Interface (SDA/GPIO2, SCL/GPIO3)
    23. 6.23 Power Supply Characteristics
    24. 6.24 Typical Characteristics
  8. Parameter Measurement Information
    1. 7.1 Parameters
      1. 7.1.1 Reference Inputs
      2. 7.1.2 Outputs
      3. 7.1.3 Serial Interface
      4. 7.1.4 Power Supply
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reference Block
        1. 8.3.1.1 Input Stages
          1. 8.3.1.1.1 Crystal Oscillator
          2. 8.3.1.1.2 LVCMOS
          3. 8.3.1.1.3 Differential AC-Coupled
        2. 8.3.1.2 Reference Mux
        3. 8.3.1.3 Reference Divider
          1. 8.3.1.3.1 Doubler
        4. 8.3.1.4 Bypass-Mux
        5. 8.3.1.5 Zero Delay, Internal and External Path
      2. 8.3.2 Phase-Locked Loop
      3. 8.3.3 Clock Distribution
        1. 8.3.3.1 Output Channel
        2. 8.3.3.2 Divider Glitch-Less Update
      4. 8.3.4 Control Pins
        1. 8.3.4.1 Global and Individual Output Enable: OE and OE_Y[4:1]
      5. 8.3.5 Operation Modes
      6. 8.3.6 Divider Synchronization - SYNC
      7. 8.3.7 EEPROM - Cyclic Redundancy Check
      8. 8.3.8 Power Supplies
        1. 8.3.8.1 Power Management
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Mode
      2. 8.4.2 Serial Interface Mode
        1. 8.4.2.1 Fall-Back Mode
    5. 8.5 Programming
      1. 8.5.1 Recommended Programming Procedure
      2. 8.5.2 EEPROM Access
      3. 8.5.3 Device Defaults
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
    4. 9.4 Initialization Setup
    5. 9.5 Power Supply Recommendations
      1. 9.5.1 Power-Up Sequence
      2. 9.5.2 De-Coupling
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Examples
  11. 10Register Maps
    1. 10.1 CDCI6214 Registers
    2. 10.2 EEPROM Map
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
      2. 11.1.2 Device Nomenclature
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • RGE|24
サーマルパッド・メカニカル・データ
発注情報

CDCI6214 Registers

Table 10-1 lists the memory-mapped registers for the CDCI6214.

Note:

All register offset addresses not listed in Table 10-1 should be considered as reserved locations and the register contents should not be modified.

Note:

All bit-field combinations not listed in the description column should be considered as reserved combinations and should only be programmed using the given values.

Table 10-1 CDCI6214 Registers
ADDRESSACRONYMREGISTER NAMESECTION
0hGENERIC0Generic setting, device operation mode, synchronization, control pins, reset, and power down.Go
1hGENERIC1Generic settings, GPIO input signal selection.Go
2hGENERIC2Generic settings, GPIO output signal selection.Go
3hGENERIC3Generic settings, EEPROM and frequency increment / decrement.Go
4hPOWER0Power-down bits, output channels.Go
5hPOWER1Power-down bits, phase-locked-loop.Go
6hSTATUS0Status information, calibration bus.Go
7hSTATUS1Status information, PLL lock and EEPROM.Go
8hSTATUS2Status information, miscellaneousGo
9hSTATUS3Status information, live CRC of EEPROMGo
AhEEPROM0EEPROM, stored CRC of EEPROMGo
BhEEPROM1EEPROM, direct access read addressGo
ChEEPROM2EEPROM, direct access read dataGo
DhEEPROM3EEPROM, direct access write addressGo
EhEEPROM4EEPROM, direct access write dataGo
FhSTARTUP0Start-up configuration, EEPROM lock, auto-calibration, and I2C glitch filterGo
10hSTARTUP1Start-up configuration, digital state machine countersGo
11hSTARTUP2Start-up configuration, digital state machine countersGo
18hREV0Revision IDGo
1AhINPUT0Input reference, buffer configuration, and crystal oscillator controls.Go
1BhINPUT1Input reference, reference divider, and bypass buffers.Go
1ChINPUT_DBG0Input reference debug, status pin buffers.Go
1DhPLL0PLL, feedback dividers.Go
1EhPLL1PLL, charge pump current and clock distribution pre-scaler dividers.Go
1FhPLL2PLL, loop filter configurationGo
21hPLL4PLL, lock detector and PFD delayGo
23hCH1_CTRL0Output channel 1, RESERVEDGo
24hCH1_CTRL1Output channel 1, RESERVEDGo
25hCH1_CTRL2Output channel 1, integer divider and mux control.Go
26hCH1_CTRL3Output channel 1, synchronization, digital delay, output buffer, mux and mute controls.Go
27hCH1_CTRL4Output channel 1, divider glitchless enable and spread spectrum controls.Go
28hCH1_CTRL5Output channel 1, RESERVEDGo
29hCH2_CTRL0Output channel 2, RESERVEDGo
2AhCH2_CTRL1Output channel 2, RESERVEDGo
2BhCH2_CTRL2Output channel 2, integer divider and mux control.Go
2ChCH2_CTRL3Output channel 2, synchronization, digital delay, output buffer, mux and mute controls.Go
2DhCH2_CTRL4Output channel 2, divider glitchless enable and spread spectrum controls.Go
2EhCH2_CTRL5Output channel 2 , RESERVEDGo
2FhCH3_CTRL0Output channel 3, RESERVEDGo
30hCH3_CTRL1Output channel 3, RESERVEDGo
31hCH3_CTRL2Output channel 3, integer divider and mux control.Go
32hCH3_CTRL3Output channel 3, synchronization, digital delay, output buffer, mux and mute controls.Go
33hCH3_CTRL4Output channel 3, divider glitchless enable and spread spectrum controls.Go
34hCH3_CTRL5Output channel 3, RESERVEDGo
35hCH4_CTRL0Output channel 4, RESERVEDGo
36hCH4_CTRL1Output channel 4, RESERVEDGo
37hCH4_CTRL2Output channel 4, integer divider and mux control.Go
38hCH4_CTRL3Output channel 4, synchronization, digital delay, output buffer, mux and mute controls.Go
39hCH4_CTRL4Output channel 4, divider glitchless enable and spread spectrum controls.Go
3AhCH4_CTRL5Output channel 4, RESERVEDGo
3BhCHX_CTRL0Output channels, generic clock distribution and bypass output controls.Go
3ChCHX_CTRL1Output channels, RESERVEDGo
3DhCHX_CTRL2Output channels, RESERVEDGo
3EhCHX_CTRL3Output channels, RESERVEDGo
3FhCHX_CTRL4Output channels, RESERVEDGo

Complex bit access types are encoded to fit into small table cells. Table 10-2 shows the codes that are used for access types in this section.

Table 10-2 CDCI6214 Access Type Codes
ACCESS TYPECODEDESCRIPTION
READ TYPE
RRRead
RCC
R
to Clear
Read
WRITE TYPE
WWWrite
WEXWWrite
WMCWWrite
WPDWWrite
WSCWWrite
WSTWWrite
RESET OR DEFAULT VALUE
-nValue after reset or the default value

10.1.1 GENERIC0 Register (Address = 0h) [reset = 0h]

GENERIC0 is shown in Figure 10-1 and described in Table 10-3.

Return to Summary Table.

Figure 10-1 GENERIC0 Register
15141312111098
i2c_a0gpio0_input_selgpio4_dir_selgpio1_dir_selgpio0_dir_selzdm_clockselRESERVEDzdm_mode
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDpll_rst_lockdetsyncrecalresetn_softswrstpowerdownmode
R/W-0hR/W-0hR/WSC-0hR/WSC-0hR/W-0hR/WSC-0hR/WPD-0hR/W-0h
Table 10-3 GENERIC0 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15i2c_a0R/W0h

When regcommit is used to program an EEPROM page, using regcommit_page, this defines the LSB of the I2C target address. When a configuration is loaded into the registers from an EEPROM page, this represents the saved LSB bit.

14gpio0_input_selR/W0h

Input signal select for GPIO0, Pin 8.

0h = RESETN

1h = SYNC

13gpio4_dir_selR/W0h

GPIO4 direction select.

0h = Input

1h = Output

12gpio1_dir_selR/W0h

GPIO1 direction select.

0h = Input

1h = Output

11gpio0_dir_selR/W0h

Direction select for Pin 8.

0h = Input

1h = Output

10zdm_clockselR/W0h

Selects the internal or external clock for calibration, in the ZDM mode. In non-ZDM mode, always internal clock will be selected and this register doesn't have any meaning.

0h = Internal Feedback

1h = External Feedback

9RESERVEDR/W0h

RESERVED

8zdm_modeR/W0h

Zero Delay Mode

0h = ZDM Off

1h = ZDM On

7RESERVEDR/W0h

RESERVED.

6pll_rst_lockdetR/W0h

Reset (active high) to PLL lock detect circuit.

5syncR/WSC0h

Generates sync pulse (for output decoder). This is a self clearing register bit and writing '1' will create the SYNC pulse.

4recalR/WSC0h

Self clearing bit. Writing '1' will do the re-calibration. For example - after the configuration followed by calibration if '1' is written to this register the calibration engine will start with the current capcode and cross code.

3resetn_softR/W0h

Configure the pin RESETN/SYNC as a soft reset.


0h = Hard Reset (reset state machines and registers)

1h = Soft Reset (state machines only, register content stays as is)

2swrstR/WSC0h

Soft reset bit. This is a self clearing bit. Writing a '0' has no effect and writing a '1' creates a reset pulse which resets the digital logic except the programmable registers. Also, this soft reset has similar effect on digital logic as hard reset (RESENTN/SYNC). Soft reset will restart the configuration and calibration.

1powerdownR/WPD0h

Analog Power Down.

0h = Active

1h = Power down

0modeR/W0h

Mode of Operation.

0h = Serial Interface, I2C

1h = Pin Mode, Output Enable

10.1.2 GENERIC1 Register (Address = 1h) [reset = 6A32h]

GENERIC1 is shown in Figure 10-2 and described in Table 10-4.

Return to Summary Table.

Figure 10-2 GENERIC1 Register
15141312111098
RESERVEDref_mux_srcref_mux
R/W-1AhR/W-0hR/W-0h
76543210
gpio4_input_selgpio1_input_sel
R/W-3hR/W-2h
Table 10-4 GENERIC1 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-10RESERVEDR/W1Ah

RESERVED

9ref_mux_srcR/W0h

Reference mux control signal source.

0h = Pin

1h = ref_mux bit-field

8ref_muxR/W0h

Reference mux bit override.

0h = XIN

1h = REF

7-4gpio4_input_selR/W3h

GPIO4 input signal select. Do not choose the same signal on gpio1_input_sel.

2h = OE

4h = OE1

5h = OE2

6h = OE3

7h = OE4

3-0gpio1_input_selR/W2h

GPIO1 input signal select.Do not choose the same signal on gpio4_input_sel.

2h = OE

4h = OE1

5h = OE2

6h = OE3

7h = OE4

10.1.3 GENERIC2 Register (Address = 2h) [reset = 53h]

GENERIC2 is shown in Figure 10-3 and described in Table 10-5.

Return to Summary Table.

Figure 10-3 GENERIC2 Register
15141312111098
RESERVEDRESERVEDRESERVEDgpio0_output_sel
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
gpio4_output_selgpio1_output_sel
R/W-5hR/W-3h
Table 10-5 GENERIC2 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-12RESERVEDR/W0h

Reserved.

11-8gpio0_output_selR/W0h

GPIO0, Pin 8, output select ,

0h = PLL_LOCK

1h = XTAL_OSC

2h = CAL_DONE

3h = CONF_DONE

4h = SYNC_DONE

5h = EEPROM_BUSY

6h = EEPROM_Y12

7h = EEPROM_M12

8h = I2C_LSB

9h = CLK_FSM

Ah = CLK_PFD_REF

Bh = CLK_PFD_FB

Ch = BUF_SYNC

Dh = BUF_SCL

Eh = BUF_SDA

7-4gpio4_output_selR/W5h

GPIO4 , output select ,

0h = PLL_LOCK

1h = XTAL_OSC

2h = CAL_DONE

3h = CONF_DONE

4h = SYNC_DONE

5h = EEPROM_BUSY

6h = EEPROM_Y12

7h = EEPROM_M12

8h = I2C_LSB

9h = CLK_FSM

Ah = CLK_PFD_REF

Bh = CLK_PFD_FB

Ch = BUF_SYNC

Dh = BUF_SCL

Eh = BUF_SDA

3-0gpio1_output_selR/W3h

GPIO1 , output select ,

0h = PLL_LOCK

1h = XTAL_OSC

2h = CAL_DONE

3h = CONF_DONE

4h = SYNC_DONE

5h = EEPROM_BUSY

6h = EEPROM_Y12

7h = EEPROM_M12

8h = I2C_LSB

9h = CLK_FSM

Ah = CLK_PFD_REF

Bh = CLK_PFD_FB

Ch = BUF_SYNC

Dh = BUF_SCL

Eh = BUF_SDA

10.1.4 GENERIC3 Register (Address = 3h) [reset = 0h]

GENERIC3 is shown in Figure 10-4 and described in Table 10-6.

Return to Summary Table.

Figure 10-4 GENERIC3 Register
15141312111098
disable_crcupdate_crcnvmcommitregcommitregcommit_pageRESERVEDRESERVEDRESERVED
R/W-0hR/WMC-0hR/WSC-0hR/WSC-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/WSC-0hR/WSC-0hR/W-0h
Table 10-6 GENERIC3 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15disable_crcR/W0h

Disable the CRC computation. However if Page is selected CRC will happen after PoR (power on reset from analog). For example- after the calibration if this bit is set to '1' and apply a soft reset (or reset through pin) the configuration will bypass the CRC computation.

14update_crcR/WMC0h

This is a self clearing register bit. Writing a '1' will cause the re-computation of CRC. The computed CRC can be read from the live CRC (nvmlcrc) register after the status bit nvmbusyh = 0.

13nvmcommitR/WSC0h

Commits contents of the EEPROM page selected by REGCOMMIT_PAGE to internal register. This register will self-clear

12regcommitR/WSC0h

Commits contents of the registers to EEPROM selected by REGCOMMIT_PAGE register. This register will self-clear.

11regcommit_pageR/W0h

Decide which page of EEPROM to use for the Register/NVM commit operations. Note= this register is used only after the initial power-up configuration from EEPROM if any. Once power-up configuration is done with the page chosen by EEPROMSEL the value of this register will be used for subsequent configurations using Register/NVM commit operations.

0h = Page 0

1h = Page 1

10-3RESERVEDR/W0h

Reserved

2-1RESERVEDR/WSC0h

Reserved

0RESERVEDR/W0h

Reserved

10.1.5 POWER0 Register (Address = 4h) [reset = 54h]

POWER0 is shown in Figure 10-5 and described in Table 10-7.

Return to Summary Table.

Figure 10-5 POWER0 Register
15141312111098
RESERVED
R/W-0h
76543210
pdn_ch4RESERVEDpdn_ch3RESERVEDpdn_ch2RESERVEDpdn_ch1RESERVED
R/W-0hR/W-1hR/W-0hR/W-1hR/W-0hR/W-1hR/W-0hR/W-0h
Table 10-7 POWER0 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-8RESERVEDR/W0h

Reserved.

7pdn_ch4R/W0h

Powers Down CH4 LDO.

0h = Active

1h = Power down

6RESERVEDR/W1h

Reserved.

5pdn_ch3R/W0h

Powers Down CH3 LDO.

0h = Active

1h = Power down

4RESERVEDR/W1h

Reserved.

3pdn_ch2R/W0h

Powers Down CH2 LDO.

0h = Active

1h = Power down

2RESERVEDR/W1h

Reserved.

1pdn_ch1R/W0h

Powers Down CH1 LDO.

0h = Active

1h = Power down

0RESERVEDR/W0h

Reserved.

10.1.6 POWER1 Register (Address = 5h) [reset = 30h]

POWER1 is shown in Figure 10-6 and described in Table 10-8.

Return to Summary Table.

Figure 10-6 POWER1 Register
15141312111098
RESERVEDpdn_pll_vcobuf2pdn_pll_vcopdn_pll_vcobuf
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
pdn_pll_cppdn_pll_lockdetpdn_pll_psfbbpdn_pll_psfbaRESERVEDpdn_pll_pfdpdn_pll_psfbpdn_ref
R/W-0hR/W-0hR/W-1hR/W-1hR/W-0hR/W-0hR/W-0hR/W-0h
Table 10-8 POWER1 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-11RESERVEDR/W0h

Reserved.

10pdn_pll_vcobuf2R/W0h

Power down of VCO buffer LDO.

0h = Active

1h = Power down

9pdn_pll_vcoR/W0h

Power down of VCO LDO.

0h = Active

1h = Power down

8pdn_pll_vcobufR/W0h

Power down of VCO buffer.

0h = Active

1h = Power down

7pdn_pll_cpR/W0h

Power down of charge pump LDO.

0h = Active

1h = Power down

6pdn_pll_lockdetR/W0h

Power down of PLL lock detector.

0h = Active

1h = Power down

5pdn_pll_psfbbR/W1h

Power down of PLL feedback pre-scaler.

0h = Active

1h = Power down

4pdn_pll_psfbaR/W1h

Active low enable of prescaler-a. Active (low) during PoR and '1' later. 1h = Power Down PFD. 0h = Otherwise.

3RESERVEDR/W0h

Reserved.

2pdn_pll_pfdR/W0h

Active low enable of PFD. Inactive (high) till calibration and '0' afterwards. 1h = Power Down PFD. 0h = Otherwise.

1pdn_pll_psfbR/W0h

Active low enable of prescaler. Active (low) during PoR and '1' later. 1h = Powers Down PS, 0h = Otherwise.

0pdn_refR/W0h

Powers Down Input Path LDO. Kill Switch. Do not use. 1h = PD, 0h = Otherwise.

10.1.7 STATUS0 Register (Address = 6h) [reset = 0h]

STATUS0 is shown in Figure 10-7 and described in Table 10-9.

Return to Summary Table.

Figure 10-7 STATUS0 Register
1514131211109876543210
cal_status
R-0h
Table 10-9 STATUS0 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-0cal_statusR0h

Calibration word.

10.1.8 STATUS1 Register (Address = 7h) [reset = 0h]

STATUS1 is shown in Figure 10-8 and described in Table 10-10.

Return to Summary Table.

Figure 10-8 STATUS1 Register
15141312111098
RESERVEDlock_det_apll_vco_cal_readynvm_rd_errornvm_wr_error
R-0hR-0hR-0hRC-0hRC-0h
76543210
rd_errorwr_errornvmcrcerrnvmbusycal_doneconfig_doneunlock_slock_det
R-0hR-0hR-0hR-0hR-0hR-0hR/WEX-0hR-0h
Table 10-10 STATUS1 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-12RESERVEDR0h

Reserved.

11lock_det_aR0hReads the PLL Lock status. 0h: PLL is Unlocked. 1h: PLL is locked.
10pll_vco_cal_readyR0h

VCO Buffer LDO POR can be read through this register.

9nvm_rd_errorRC0h

Occurs when any NVM operation is issued during Read Phase of the NVM. The Read Phase of the NVM includes CRC calculation or a simple read through RD NVM Addr/Data registers from any NVM location or a NVM commit operation.

8nvm_wr_errorRC0h

Occurs when any NVM operation is issued during Write Phase of the NVM. Write Phase of the NVM includes a simple write into any NVM location through WR NVM Addr/Data registers or a Register Commit operation.

7rd_errorR0h

Reading using the I2C interface with an address above the address of the last register gives this error.

6wr_errorR0h

Writing using the I2C interface with an address above the address of the last register gives this error.

5nvmcrcerrR0h

NVM CRC Error Indication. The NVMCRCERR bit is set to 1 if a CRC Error has been detected when reading back from on-chip EEPROM during device configuration. This bit will be cleared when NVMCOMMIT is submitted or Update CRC is issued.

4nvmbusyR0h

NVM Program Busy Indication. The NVMBUSY bit is 1 during an on-chip EEPROM Erase/Program cycle. While NVMBUSY is 1 the on-chip EEPROM cannot be accessed. When the NVM operation is completed this bit will be cleared. NVM related operations are REGcommit NVMcommit CRC calculation or simple Read/Write through RD/WR NVM.

3cal_doneR0h

1h = Calibration (Two rounds of Amplitude followed by calibration) is done.

2config_doneR0h

1 h = Configuration (CRC Check followed by transfer of EEPROM to registers) is done.

1unlock_sR/WEX0h

Lock Detect Sticky Bit. This indicates the loss of lock of the PLL and this is cleared only by recalibration or a hard reset through RESETN/SYNC pin

0h = locked

1h = unlocked

0lock_detR0h

When the calibration is done frequency may or may not be locked. 1h = Frequency is locked. 0h = Otherwise

0h = unlocked

1h = locked

10.1.9 STATUS2 Register (Address = 8h) [reset = 0h]

STATUS2 is shown in Figure 10-9 and described in Table 10-11.

Return to Summary Table.

Figure 10-9 STATUS2 Register
1514131211109876543210
misc_status
R-0h
Table 10-11 STATUS2 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-0misc_statusR0h

Miscellaneous status word.

10.1.10 STATUS3 Register (Address = 9h) [reset = 0h]

STATUS3 is shown in Figure 10-10 and described in Table 10-12.

Return to Summary Table.

Figure 10-10 STATUS3 Register
1514131211109876543210
nvmlcrc
R-0h
Table 10-12 STATUS3 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-0nvmlcrcR0h

The NVMLCRC register holds the Live CRC byte that has been calculated while reading on-chip EEPROM.

10.1.11 EEPROM0 Register (Address = Ah) [reset = 0h]

EEPROM0 is shown in Figure 10-11 and described in Table 10-13.

Return to Summary Table.

Figure 10-11 EEPROM0 Register
1514131211109876543210
nvmscrc
R-0h
Table 10-13 EEPROM0 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-0nvmscrcR0h

Stored CRC value. This value is used to compare with the computed CRC and to update the CRC Status bit

10.1.12 EEPROM1 Register (Address = Bh) [reset = 0h]

EEPROM1 is shown in Figure 10-12 and described in Table 10-14.

Return to Summary Table.

Figure 10-12 EEPROM1 Register
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDnvm_rd_addr
R/W-0hR/W-0h
Table 10-14 EEPROM1 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-6RESERVEDR/W0h

Reserved.

5-0nvm_rd_addrR/W0h

Writing an address into the NVM WR Address starts the read loop. This register will contain the data read from the EEPROM at the address provided by the NVM WR Address. The address is auto-incremented and subsequent read from the NVM RD Data register will give the data from the next EEPROM location.

10.1.13 EEPROM2 Register (Address = Ch) [reset = 0h]

EEPROM2 is shown in Figure 10-13 and described in Table 10-15.

Return to Summary Table.

Figure 10-13 EEPROM2 Register
1514131211109876543210
nvm_rd_data
R-0h
Table 10-15 EEPROM2 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-0nvm_rd_dataR0h

Reading from this register will return the data present at the EEPROM from the immediate next address location than what was programmed in the NVM RD Address register since writing into NVM RD Address register already returned the data from EEPROM from the written address. Subsequent read from this register will cause the address to be auto-incremented and cause a read from the next EEPROM location.

10.1.14 EEPROM3 Register (Address = Dh) [reset = 0h]

EEPROM3 is shown in Figure 10-14 and described in Table 10-16.

Return to Summary Table.

Figure 10-14 EEPROM3 Register
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDnvm_wr_addr
R/W-0hR/W-0h
Table 10-16 EEPROM3 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-6RESERVEDR/W0h

Reserved.

5-0nvm_wr_addrR/W0h

Writing an address into the NVM WR Address starts the write loop. But Writing a data into the NVM WR Data register will program the EEPROM with that data at the address provided by writing into NVM WR Address initially.

10.1.15 EEPROM4 Register (Address = Eh) [reset = 0h]

EEPROM4 is shown in Figure 10-15 and described in Table 10-17.

Return to Summary Table.

Figure 10-15 EEPROM4 Register
1514131211109876543210
nvm_wr_data
R/W-0h
Table 10-17 EEPROM4 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-0nvm_wr_dataR/W0h

Writing a data into this register will program the EEPROM with the written data at the address given by NVM WR Address. Subsequent write into this register will cause the address to be auto-incremented and cause a program at the next EEPROM location.

10.1.16 STARTUP0 Register (Address = Fh) [reset = 37h]

STARTUP0 is shown in Figure 10-16 and described in Table 10-18.

Return to Summary Table.

Figure 10-16 STARTUP0 Register
15141312111098
ee_lockRESERVEDzdm_auto
R/W-0hR/W-0hR/W-0h
76543210
bypass_calbypass_configcal_muteshift_leftgpio3_gf_engpio2_gf_enacal_en
R/W-0hR/W-0hR/W-1hR/W-2hR/W-1hR/W-1hR/W-1h
Table 10-18 STARTUP0 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-12ee_lockR/W0h

Locks EEPROM for regcommit and EEPROM write operations. To unlock, write 5h, any other value to lock.

11-9RESERVEDR/W0h

Reserved.

8zdm_autoR/W0h

Setting this bit 1 will allow state machine to control the value of pll_ndiv and pll_psfb internally in Normal/ZDM mode of calibration. If set 0 the user has to manually program the pll_ndiv and pll_psfb

7bypass_calR/W0h

Bypass the calibration. By default two rounds of calibrations (AC followed by FC) will be done. Setting this bit to 1 will bypass the calibration.

6bypass_configR/W0h

Bypass the configuration. Note that on PoR this bit is zero and hence configuration will happen. However after the first configuration this bit can be set and apply the soft/pin reset so that configuration will be bypassed.

5cal_muteR/W1h

Mute the output during the calibration.

0h = Outputs stay active

1h = Outputs muted

4-3shift_leftR/W2h

Divide the ref clock (PFD clock) during calibration by 2 to the power of value

0h = 1

1h = 2

2h = 4

3h = 8

2gpio3_gf_enR/W1h

Enable the glitch filter for SCL, GPIO3.

0h = Disabled

1h = Enabled

1gpio2_gf_enR/W1h

Enable the glitch filter for SDA, GPIO2.

0h = Disabled

1h = Enabled

0acal_enR/W1h

Enable automatic frequency calibration at power-up or EEPROM re-load.

0h = Disabled

1h = Enabled

10.1.17 STARTUP1 Register (Address = 10h) [reset = 921Fh]

STARTUP1 is shown in Figure 10-17 and described in Table 10-19.

Return to Summary Table.

Figure 10-17 STARTUP1 Register
15141312111098
pll_lock_dlyac_init_dly
R/W-12hR/W-10h
76543210
ac_init_dlycp_dly
R/W-10hR/W-1Fh
Table 10-19 STARTUP1 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-11pll_lock_dlyR/W12h

Wait time before lock detect goes high after the calibration. Expected value is approximately 1 ms. The actual delay will be 4 × T × {programmed value} where T = 200ns typically.

10-5ac_init_dlyR/W10h

Peak detector settlig time, that is, pll_en_peakdet_vco going high to first cross code change. Expected value is 1.6 µs. The actual delay will be 4 × T × {programmed value} where T = 200ns typically.

4-0cp_dlyR/W1Fh

Delay from vtune driver enable (pll_en_vtune_drv) going high to peak detector enable (pll_en_peakdet_vco) going high. Expected delay is 200 µs. The actual delay will be 64 × T × {programmed value} where T = 200ns typically.

10.1.18 STARTUP2 Register (Address = 11h) [reset = 6C4h]

STARTUP2 is shown in Figure 10-18 and described in Table 10-20.

Return to Summary Table.

Figure 10-18 STARTUP2 Register
15141312111098
RESERVEDswitch_dlyerr_cnt
R/W-0hR/W-0hR/W-6h
76543210
fc_setl_dlyac_cmp_dly
R/W-3hR/W-4h
Table 10-20 STARTUP2 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15RESERVEDR/W0h

Reserved.

14-11switch_dlyR/W0h

Indicates number of digital clocks to wait before SSM clock is turned off after all the active signals are low. Internally scaled up by 26. Digital clock period is 200ns typically.

10-8err_cntR/W6h

Indicates how long to wait for before declaring lock detect. In PFD clocks period.

0h = 32

1h = 64

2h = 128

3h = 256

7-6fc_setl_dlyR/W3h

Delay between two cap codes in terms of REFCLK period. Expected value is 1 µs. The actual delay will be 32 × T × {programmed value} where T is the refclk period.

5-0ac_cmp_dlyR/W4h

Delay between successive cross code change. Expected value is 1 µs. The actual delay will be 4 × T × {programmed value} where T = 200ns typically.

10.1.19 REV0 Register (Address = 18h) [reset = 601h]

REV0 is shown in Figure 10-19 and described in Table 10-21.

Return to Summary Table.

Figure 10-19 REV0 Register
15141312111098
RESERVED
R/W-6h
76543210
rev_reg
R-1h
Table 10-21 REV0 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-8ReservedR06hReserved
7-0rev_regR1h

Revision ID register.

1h = CDCI6214

10.1.20 INPUT0 Register (Address = 1Ah) [reset = B14h]

INPUT0 is shown in Figure 10-20 and described in Table 10-22.

Return to Summary Table.

Figure 10-20 INPUT0 Register
15141312111098
ref_inbuf_ctrlRESERVEDRESERVEDip_xo_cload
R/W-0hR/W-0hR/W-0hR/W-Bh
76543210
RESERVEDip_xo_gmxin_inbuf_ctrl
R/W-0hR/W-5hR/W-0h
Table 10-22 INPUT0 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15ref_inbuf_ctrlR/W0h

Reference input buffer select.

0h = LVCMOS

1h = AC-Differential

14RESERVEDR/W0hRESERVED
13RESERVEDR/W0hRESERVED
12-8ip_xo_cloadR/WBh

Selects load cap for XO (up to 9 pF) in 5 bit binary selection). Step size is about 200 fF.

0h = 3.0 pF

1h = 3.2 pF

2h = 3.4 pF

3h = 3.6 pF

4h = 3.8 pF

5h = 4.0 pF

6h = 4.2 pF

7h = 4.4 pF

8h = 4.6 pF

9h = 4.8 pF

Ah = 5.0 pF

Bh = 5.2 pF

Ch = 5.4 pF

Dh = 5.6 pF

Eh = 5.8 pF

Fh = 6.0 pF

10h = 6.2 pF

11h = 6.4 pF

12h = 6.5 pF

13h = 6.7 pF

14h = 6.9 pF

15h = 7.1 pF

16h = 7.3 pF

17h = 7.5 pF

18h = 7.7 pF

19h = 7.9 pF

1Ah = 8.1 pF

1Bh = 8.3 pF

1Ch = 8.5 pF

1Dh = 8.7 pF

1Eh = 8.9 pF

1Fh = 9.0 pF

7-6RESERVEDR/W0hRESERVED
5-2ip_xo_gmR/W5h

Tune bias current for XO. Gm programmability. Typical values:

0h = Disabled

1h = 14 µA

2h = 29 µA

3h = 44 µA

4h = 59 µA

5h = 148 µA

6h = 295 µA

7h = 443 µA

8h = 591 µA

9h = 884 µA

Ah = 1177 µA

Bh = 1468 µA

Ch = 1758 µA

1-0xin_inbuf_ctrlR/W0h

Input buffer select.

0h = XO

1h = CMOS

2h = DIFF

10.1.21 INPUT1 Register (Address = 1Bh) [reset = 0h]

INPUT1 is shown in Figure 10-21 and described in Table 10-23.

Return to Summary Table.

Figure 10-21 INPUT1 Register
15141312111098
RESERVEDip_byp_en_ch4ip_byp_en_ch3ip_byp_en_ch2ip_byp_en_ch1ip_byp_en_y0ip_byp_muxip_rst_rdiv
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
ip_rdiv
R/W-0h
Table 10-23 INPUT1 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15RESERVEDR/W0h

RESERVED

14ip_byp_en_ch4R/W0h

Bypass path buffer enable for CH4. This is required to drive a bypass signal using ch4_iod_mux.

0h = disabled

1h = enabled

13ip_byp_en_ch3R/W0h

Bypass path buffer enable for CH3. This is required to drive a bypass signal using ch3_iod_mux.

0h = disabled

1h = enabled

12ip_byp_en_ch2R/W0h

Bypass path buffer enable for CH2. This is required to drive a bypass signal using ch2_iod_mux.

0h = disabled

1h = enabled

11ip_byp_en_ch1R/W0h

Bypass path buffer enable for CH1. This is required to drive a bypass signal using ch1_iod_mux.

0h = disabled

1h = enabled

10ip_byp_en_y0R/W0h

Enable input clock to come out on Y0 buffer.

9ip_byp_muxR/W0h

Selects Y0 clock between "REF_CLK" and "PFD_CLK".

0h = REF

1h = PFD

8ip_rst_rdivR/W0h

Resets flops in ref divider. Active (high) during power on reset or SWRST or pin reset and inactive afterwards.

7-0ip_rdivR/W0h

Reference clock divider. 0 = Doubler ON, 1 = /1, 2 = /2. and so forth.

0h = x2

1h = /1

2h = /2

3h = /3

4h = /4

5h = /5

...

FFh = /255

10.1.22 INPUT_DBG0 Register (Address = 1Ch) [reset = 0h]

INPUT_DBG0 is shown in Figure 10-22 and described in Table 10-24.

Return to Summary Table.

Figure 10-22 INPUT_DBG0 Register
15141312111098
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 10-24 INPUT_DBG0 Register Field Descriptions
BitFieldTypeResetDescription
15-6RESERVEDR/W0h

RESERVED.

5RESERVEDR/W0h

RESERVED

4RESERVEDR/W0h

RESERVED

3RESERVEDR/W0h

RESERVED

2RESERVEDR/W0h

RESERVED

1RESERVEDR/W0h

RESERVED

0RESERVEDR/W0h

RESERVED

10.1.23 PLL0 Register (Address = 1Dh) [reset = Ch]

PLL0 is shown in Figure 10-23 and described in Table 10-25.

Return to Summary Table.

Figure 10-23 PLL0 Register
15141312111098
pll_psfbpll_ndiv
R/W-0hR/W-Ch
76543210
pll_ndiv
R/W-Ch
Table 10-25 PLL0 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-14pll_psfbR/W0h

Programming bits for PLL feedback pre-scaler.

0h = /4

1h = /5

2h = /6

13-0pll_ndivR/WCh

Feedback divider, must be at least 6h.

10.1.24 PLL1 Register (Address = 1Eh) [reset = 5140h]

PLL1 is shown in Figure 10-24 and described in Table 10-26.

Return to Summary Table.

Figure 10-24 PLL1 Register
15141312111098
pll_cp_uppll_cp_dn
R/W-14hR/W-14h
76543210
pll_cp_dnpll_psbpll_psa
R/W-14hR/W-0hR/W-0h
Table 10-26 PLL1 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-10pll_cp_upR/W14h

Programming bits for up current of CP.

0h = 0.0 mA

1h = 0.1 mA

2h = 0.2 mA

3h = 0.3 mA

[...]

1Fh = 3.1 mA

37h = 3.2 mA

38h = 3.3 mA

[...]

3Dh = 3.8 mA

3Eh = 3.9 mA

3Fh = 4.0 mA

9-4pll_cp_dnR/W14h

Programming bits for down current of CP.

0h = 0.0 mA

1h = 0.1 mA

2h = 0.2 mA

3h = 0.3 mA

[...]

1Fh = 3.1 mA

37h = 3.2 mA

38h = 3.3 mA

[...]

3Dh = 3.8 mA

3Eh = 3.9 mA

3Fh = 4.0 mA

3-2pll_psbR/W0h

Programming bits for pre-scaler B.

0h = /4

1h = /5

2h = /6

1-0pll_psaR/W0h

Programming bits for pre-scaler A.

0h = /4

1h = /5

2h = /6

10.1.25 PLL2 Register (Address = 1Fh) [reset = 1E72h]

PLL2 is shown in Figure 10-25 and described in Table 10-27.

Return to Summary Table.

Figure 10-25 PLL2 Register
15141312111098
RESERVEDpll_lf_zcappll_lf_res
R/W-0hR/W-FhR/W-3h
76543210
pll_lf_respll_lf_pcap
R/W-3hR/W-12h
Table 10-27 PLL2 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-14RESERVEDR/W0h

RESERVED.

13-9pll_lf_zcapR/WFh

Programming bits of cap value of zero of loop-filter.

0h = 000 pF

1h = 030 pF

2h = 060 pF

3h = 090 pF

4h = 120 pF

5h = 150 pF

6h = 180 pF

7h = 210 pF

8h = 240 pF

9h = 270 pF

Ah = 300 pF

Bh = 330 pF

Ch = 360 pF

Dh = 390 pF

Eh = 420 pF

Fh = 450 pF

10h = 480 pF

11h = 510 pF

12h = 540 pF

13h = 570 pF

14h = 600 pF

8-5pll_lf_resR/W3h

Programming bits of res value of zero of loop-filter.

0h = open kΩ

1h = 00.5 kΩ

2h = 01.5 kΩ

3h = 02.5 kΩ

4h = 03.5 kΩ

5h = 04.5 kΩ

6h = 05.5 kΩ

7h = 06.5 kΩ

8h = 07.5 kΩ

9h = 08.5 kΩ

Ah = 09.5 kΩ

Bh = 10.5 kΩ

Ch = 11.5 kΩ

4-0pll_lf_pcapR/W12h

Programming bits of cap value of pole of loop-filter.

0h = 00.0 pF

1h = 00.5 pF

2h = 01.5 pF

3h = 02.5 pF

4h = 03.5 pF

5h = 04.5 pF

6h = 05.5 pF

7h = 06.5 pF

8h = 07.5 pF

9h = 08.5 pF

Ah = 09.5 pF

Bh = 10.5 pF

Ch = 11.5 pF

Dh = 12.5 pF

Eh = 13.5 pF

Fh = 14.5 pF

10h = 15.5 pF

11h = 16.5 pF

12h = 17.5 pF

13h = 18.5 pF

14h = 19.5 pF

10.1.26 PLL4 Register (Address = 21h) [reset = 7h]

PLL4 is shown in Figure 10-26 and described in Table 10-28.

Return to Summary Table.

Figure 10-26 PLL4 Register
15141312111098
RESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDpll_pfd_dly_ctrlpll_lockdet_windowpll_lockdet_wait
R/W-0hR/W-0hR/W-1hR/W-3h
Table 10-28 PLL4 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-7RESERVEDR/W0h

Reserved.

6-5pll_pfd_dly_ctrlR/W0h

Programming of PFD reset delay. In PFD period.

0h = 2

1h = 6

2h = 10

3h = 14

4-2pll_lockdet_windowR/W1h

Programmability of PFD input and output time window for lock detect.

0h = disabled

1h = typical 1.4 ns

2h = typical 2.6 ns

3h = typical 3.9 ns

4h = typical 5.2 ns

5h = typical 6.4 ns

6h = typical 7.6 ns

7h = typical 8.9 ns

1-0pll_lockdet_waitR/W3h

Programmability of analog lock detect timer. In PFD cycles

0h = 1

1h = 16

2h = 64

3h = 128

10.1.27 CH1_CTRL0 Register (Address = 23h) [reset = 8000h]

CH1_CTRL0 is shown in Figure 10-27 and described in Table 10-29.

Return to Summary Table.

Figure 10-27 CH1_CTRL0 Register
1514131211109876543210
RESERVED
R/WEX-8000h
Table 10-29 CH1_CTRL0 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-0RESERVEDR/WEX8000h

RESERVED

10.1.28 CH1_CTRL1 Register (Address = 24h) [reset = 0h]

CH1_CTRL1 is shown in Figure 10-28 and described in Table 10-30.

Return to Summary Table.

Figure 10-28 CH1_CTRL1 Register
15141312111098
RESERVEDRESERVED
R/W-0hR/WEX-0h
76543210
RESERVED
R/WEX-0h
Table 10-30 CH1_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR/W0h

RESERVED.

8-0RESERVEDR/WEX0h

RESERVED.

10.1.29 CH1_CTRL2 Register (Address = 25h) [reset = 8003h]

CH1_CTRL2 is shown in Figure 10-29 and described in Table 10-31.

Return to Summary Table.

Figure 10-29 CH1_CTRL2 Register
15141312111098
ch1_iod_muxch1_iod_div
R/W-2hR/WEX-3h
76543210
ch1_iod_div
R/WEX-3h
Table 10-31 CH1_CTRL2 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-14ch1_iod_muxR/W2h

Input Clock selection for IOD.

0h = PSA

1h = PSB

3h = REF

13-0ch1_iod_divR/WEX3h

IOD Division Value. 0h = Powers Down, Output=Input/IOD_DIV

10.1.30 CH1_CTRL3 Register (Address = 26h) [reset = 9h]

CH1_CTRL3 is shown in Figure 10-30 and described in Table 10-32.

Return to Summary Table.

Figure 10-30 CH1_CTRL3 Register
15141312111098
ch1_sync_delaych1_sync_enRESERVEDch1_mute_sel
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
ch1_mutech1_cmos_polch1_outbuf_ctrlch1_mux
R/W-0hR/W-0hR/W-2hR/W-1h
Table 10-32 CH1_CTRL3 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-11ch1_sync_delayR/W0h

Sync Delay cycles of IOD Input Clock. One cycle is a period of the selected pre-scaler clock.

10ch1_sync_enR/W0h

Enables SYNC for the channel.

0h = Disabled

1h = Enabled

9RESERVEDR/W0h

Reserved.

8ch1_mute_selR/W0h

Mute selection for Output Channel.

0h = P=L N=H

1h = P=H N=L

7ch1_muteR/W0h

To mute the output on this channel.

0h = Un-mutes the output. 1h = mutes the output.
4-2ch1_outbuf_ctrlR/W2h

Select the output buffer format.

0h = disabled

1h = LVDS (1)

2h = HCSL

3h = CML

4h = LVPECL

1-0ch1_muxR/W1h

Output Clock Selection.

1h = CH1

2h = CH2

For DC-connection program chx_lvds_cmtrim_inc = 0 and ch[4:1]_1p8vdet in Table 10-53 and Table 10-52 accordingly.

10.1.31 CH1_CTRL4 Register (Address = 27h) [reset = 679h]

CH1_CTRL4 is shown in Figure 10-31 and described in Table 10-33.

Return to Summary Table.

Figure 10-31 CH1_CTRL4 Register
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-3hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDch1_glitchless_en
R/W-1hR/W-3hR/W-1hR/W-0hR/W-0hR/W-1h
Table 10-33 CH1_CTRL4 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR/W0h

RESERVED

11-9RESERVEDR/W3h

RESERVED

8RESERVEDR/W0h

RESERVED

7-6RESERVEDR/W1h

RESERVED

5-4RESERVEDR/W3h

RESERVED

3RESERVEDR/W1h

RESERVED

2RESERVEDR/W0h

RESERVED

1RESERVEDR/W0h

RESERVED

0ch1_glitchless_enR/W1h

Enables Glitchless switching for Output Channel.

0h = Immediate

1h = Glitchless

10.1.32 CH1_CTRL5 Register (Address = 28h) [reset = 8h]

CH1_CTRL5 is shown in Figure 10-32 and described in Table 10-34.

Return to Summary Table.

Figure 10-32 CH1_CTRL5 Register
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDch1_1p8vdetRESERVEDRESERVEDRESERVED
R/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
Table 10-34 CH1_CTRL5 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-4RESERVEDR/W0h

RESERVED.

3ch1_1p8vdetR/W1h

Specify supply on the channel.

0h = 2.5 V or 3.3 V

1h = 1.8 V

2-0RESERVEDR/W0h

RESERVED

10.1.33 CH2_CTRL0 Register (Address = 29h) [reset = 8000h]

CH2_CTRL0 is shown in Figure 10-33 and described in Table 10-35.

Return to Summary Table.

Figure 10-33 CH2_CTRL0 Register
1514131211109876543210
RESERVED
R/WEX-8000h
Table 10-35 CH2_CTRL0 Register Field Descriptions
BitFieldTypeResetDescription
15-0RESERVEDR/WEX8000h

RESERVED

10.1.34 CH2_CTRL1 Register (Address = 2Ah) [reset = 0h]

CH2_CTRL1 is shown in Figure 10-34 and described in Table 10-36.

Return to Summary Table.

Figure 10-34 CH2_CTRL1 Register
15141312111098
RESERVEDRESERVED
R/W-0hR/WEX-0h
76543210
RESERVED
R/WEX-0h
Table 10-36 CH2_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR/W0h

RESERVED.

8-0RESERVEDR/WEX0h

RESERVED.

10.1.35 CH2_CTRL2 Register (Address = 2Bh) [reset = 0h]

CH2_CTRL2 is shown in Figure 10-35 and described in Table 10-37.

Return to Summary Table.

Figure 10-35 CH2_CTRL2 Register
15141312111098
ch2_iod_muxch2_iod_div
R/W-0hR/WEX-0h
76543210
ch2_iod_div
R/WEX-0h
Table 10-37 CH2_CTRL2 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-14ch2_iod_muxR/W0h

Input Clock selection for IOD.

0h = PSA

1h = PSB

3h = REF

13-0ch2_iod_divR/WEX0h

IOD Division Value. 0h = Powers Down, Output = Input/IOD_DIV

10.1.36 CH2_CTRL3 Register (Address = 2Ch) [reset = 8h]

CH2_CTRL3 is shown in Figure 10-36 and described in Table 10-38.

Return to Summary Table.

Figure 10-36 CH2_CTRL3 Register
15141312111098
ch2_sync_delaych2_sync_enRESERVEDch2_mute_sel
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
ch2_mutech2_cmos_polch2_outbuf_ctrlch2_mux
R/W-0hR/W-0hR/W-2hR/W-0h
Table 10-38 CH2_CTRL3 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-11ch2_sync_delayR/W0h

Sync Delay cycles of IOD Input Clock. One cycle is a period of the selected pre-scaler clock.

10ch2_sync_enR/W0h

Enables SYNC for the channel.

0h = Disabled

1h = Enabled

9RESERVEDR/W0h

RESERVED.

8ch2_mute_selR/W0h

Mute selection for Output Channel.

0h = P=L N=H

1h = P=H N=L

7ch2_muteR/W0h

To mute the output on this channel.

0h = Un-mutes the output. 1h = mutes the output.
6-5ch2_cmos_polR/W0h

programmability of output CMOS buffer polarity.

0h = P+ N+

1h = P+ N–

2h = P– N+

3h = P– N–

4-2ch2_outbuf_ctrlR/W2h

Select the output buffer format.

0h = disabled

1h = LVDS(1)

2h = HCSL

3h = CML

4h = LVPECL

5h = CMOSPN

6h = CMOSP

7h = CMOSN

1-0ch2_muxR/W0h

Output Clock Selection.

0h = CH1

1h = CH2

2h = CH3

For DC-connection program chx_lvds_cmtrim_inc = 0 and ch[4:1]_1p8vdet in Table 10-53 and Table 10-52 accordingly.

10.1.37 CH2_CTRL4 Register (Address = 2Dh) [reset = 71h]

CH2_CTRL4 is shown in Figure 10-37 and described in Table 10-39.

Return to Summary Table.

Figure 10-37 CH2_CTRL4 Register
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDch2_glitchless_en
R/W-1hR/W-3hR/W-0hR/W-0hR/W-0hR/W-1h
Table 10-39 CH2_CTRL4 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR/W0h

RESERVED

11-8RESERVEDR/W0h

RESERVED

7-6RESERVEDR/W1h

RESERVED

5-4RESERVEDR/W3h

RESERVED

3-1RESERVEDR/W0h

RESERVED

0ch2_glitchless_enR/W1h

Enables Glitchless switching for Output Channel.

0h = Immediate

1h = Glitchless

10.1.38 CH2_CTRL5 Register (Address = 2Eh) [reset = 8h]

CH2_CTRL5 is shown in Figure 10-38 and described in Table 10-40.

Return to Summary Table.

Figure 10-38 CH2_CTRL5 Register
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDch2_1p8vdetRESERVEDRESERVEDRESERVED
R/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
Table 10-40 CH2_CTRL5 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-4RESERVEDR/W0h

RESERVED.

3ch2_1p8vdetR/W1h

Specify supply on the channel.

0h = 2.5 V or 3.3 V

1h = 1.8 V

2-0RESERVEDR/W0h

RESERVED

10.1.39 CH3_CTRL0 Register (Address = 2Fh) [reset = 8000h]

CH3_CTRL0 is shown in Figure 10-39 and described in Table 10-41.

Return to Summary Table.

Figure 10-39 CH3_CTRL0 Register
1514131211109876543210
RESERVED
R/WEX-8000h
Table 10-41 CH3_CTRL0 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-0RESERVEDR/WEX8000h

RESERVED

10.1.40 CH3_CTRL1 Register (Address = 30h) [reset = 0h]

CH3_CTRL1 is shown in Figure 10-40 and described in Table 10-42.

Return to Summary Table.

Figure 10-40 CH3_CTRL1 Register
15141312111098
RESERVEDRESERVED
R/W-0hR/WEX-0h
76543210
RESERVED
R/WEX-0h
Table 10-42 CH3_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR/W0h

RESERVED.

8-0RESERVEDR/WEX0h

RESERVED

10.1.41 CH3_CTRL2 Register (Address = 31h) [reset = 0h]

CH3_CTRL2 is shown in Figure 10-41 and described in Table 10-43.

Return to Summary Table.

Figure 10-41 CH3_CTRL2 Register
15141312111098
ch3_iod_muxch3_iod_div
R/W-0hR/WEX-0h
76543210
ch3_iod_div
R/WEX-0h
Table 10-43 CH3_CTRL2 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-14ch3_iod_muxR/W0h

Input Clock selection for IOD.

0h = PSA

1h = PSB

3h = REF

13-0ch3_iod_divR/WEX0h

IOD Division Value. 0h = Powers Down, Output=Input/IOD_DIV

10.1.42 CH3_CTRL3 Register (Address = 32h) [reset = 4h]

CH3_CTRL3 is shown in Figure 10-42 and described in Table 10-44.

Return to Summary Table.

Figure 10-42 CH3_CTRL3 Register
15141312111098
ch3_sync_delaych3_sync_enRESERVEDch3_mute_sel
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
ch3_mutech3_cmos_polch3_outbuf_ctrlch3_mux
R/W-0hR/W-0hR/W-1hR/W-0h
Table 10-44 CH3_CTRL3 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-11ch3_sync_delayR/W0h

Sync Delay cycles of IOD Input Clock. One cycle is a period of the selected pre-scaler clock.

10ch3_sync_enR/W0h

Enables SYNC for the channel.

0h = Disabled

1h = Enabled

9RESERVEDR/W0h

RESERVED.

8ch3_mute_selR/W0h

Mute selection for Output Channel.

0h = P=L N=H

1h = P=H N=L

7ch3_muteR/W0h

To mute the output on this channel.

0h = Un-mutes the output. 1h = mutes the output.
6-5ch3_cmos_polR/W0h

programmability of output CMOS buffer polarity.

0h = P+ N+

1h = P+ N–

2h = P– N+

3h = P– N–

4-2ch3_outbuf_ctrlR/W1h

Select the output buffer format.

0h = disabled

1h = LVDS(1)

2h = HCSL

3h = CML

4h = LVPECL

5h = CMOSPN

6h = CMOSP

7h = CMOSN

1-0ch3_muxR/W0h

Output Clock Selection.

0h = CH2

1h = CH3

2h = CH4

For DC-connection program chx_lvds_cmtrim_inc = 0 and ch[4:1]_1p8vdet in Table 10-53 and Table 10-52 accordingly.

10.1.43 CH3_CTRL4 Register (Address = 33h) [reset = 671h]

CH3_CTRL4 is shown in Figure 10-43 and described in Table 10-45.

Return to Summary Table.

Figure 10-43 CH3_CTRL4 Register
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-3hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDch3_glitchless_en
R/W-1hR/W-3hR/W-0hR/W-0hR/W-0hR/W-1h
Table 10-45 CH3_CTRL4 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR/W0h

RESERVED

11-9RESERVEDR/W3h

RESERVED

8RESERVEDR/W0h

RESERVED

7-6RESERVEDR/W1h

RESERVED

5-4RESERVEDR/W3h

RESERVED

3-1RESERVEDR/W0h

RESERVED

0ch3_glitchless_enR/W1h

Enables Glitchless switching for Output Channel.

0h = Immediate

1h = Glitchless

10.1.44 CH3_CTRL5 Register (Address = 34h) [reset = 8h]

CH3_CTRL5 is shown in Figure 10-44 and described in Table 10-46.

Return to Summary Table.

Figure 10-44 CH3_CTRL5 Register
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDch3_1p8vdetRESERVEDRESERVEDRESERVED
R/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
Table 10-46 CH3_CTRL5 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-4RESERVEDR/W0h

RESERVED.

3ch3_1p8vdetR/W1h

Specify supply on the channel.

0h = 2.5 V or 3.3 V

1h = 1.8 V

2-0RESERVEDR/W0h

RESERVED

10.1.45 CH4_CTRL0 Register (Address = 35h) [reset = 8000h]

CH4_CTRL0 is shown in Figure 10-45 and described in Table 10-47.

Return to Summary Table.

Figure 10-45 CH4_CTRL0 Register
1514131211109876543210
RESERVED
R/WEX-8000h
Table 10-47 CH4_CTRL0 Register Field Descriptions
BitFieldTypeResetDescription
15-0RESERVEDR/WEX8000h

RESERVED

10.1.46 CH4_CTRL1 Register (Address = 36h) [reset = 0h]

CH4_CTRL1 is shown in Figure 10-46 and described in Table 10-48.

Return to Summary Table.

Figure 10-46 CH4_CTRL1 Register
15141312111098
RESERVEDRESERVED
R/W-0hR/WEX-0h
76543210
RESERVED
R/WEX-0h
Table 10-48 CH4_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
15-9RESERVEDR/W0h

RESERVED.

8-0RESERVEDR/WEX0h

RESERVED

10.1.47 CH4_CTRL2 Register (Address = 37h) [reset = 0h]

CH4_CTRL2 is shown in Figure 10-47 and described in Table 10-49.

Return to Summary Table.

Figure 10-47 CH4_CTRL2 Register
15141312111098
ch4_iod_muxch4_iod_div
R/W-0hR/WEX-0h
76543210
ch4_iod_div
R/WEX-0h
Table 10-49 CH4_CTRL2 Register Field Descriptions
BitFieldTypeResetDescription
15-14ch4_iod_muxR/W0h

Input Clock selection for IOD.

0h = PSA

1h = PSB

3h = REF

13-0ch4_iod_divR/WEX0h

IOD Division Value. 0h = Powers Down, Output=Input/IOD_DIV.

10.1.48 CH4_CTRL3 Register (Address = 38h) [reset = 4h]

CH4_CTRL3 is shown in Figure 10-48 and described in Table 10-50.

Return to Summary Table.

Figure 10-48 CH4_CTRL3 Register
15141312111098
ch4_sync_delaych4_sync_enRESERVEDch4_mute_sel
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
ch4_mutech4_cmos_polch4_outbuf_ctrlch4_mux
R/W-0hR/W-0hR/W-1hR/W-0h
Table 10-50 CH4_CTRL3 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-11ch4_sync_delayR/W0h

Sync Delay cycles of IOD Input Clock. One cycle is a period of the selected pre-scaler clock.

10ch4_sync_enR/W0h

Enables SYNC for the channel.

0h = Disabled

1h = Enabled

9RESERVEDR/W0h

RESERVED.

8ch4_mute_selR/W0h

Mute selection for Output Channel.

0h = P=L N=H

1h = P=H N=L

7ch4_muteR/W0h

To mute the output on this channel.

0h = Un-mutes the output. 1h = mutes the output.
4-2ch4_outbuf_ctrlR/W1h

Select the output buffer format.

0h = disabled

1h = LVDS(1)

2h = HCSL

3h = CML

4h = LVPECL

1-0ch4_muxR/W0h

Output Clock Selection. 0h = Previous Channel, 1h = Current Channel, 2h = Next Channel, 3h = AGND

0h = CH3

1h = CH4

For DC-connection program chx_lvds_cmtrim_inc = 0 and ch[4:1]_1p8vdet in Table 10-53 and Table 10-52 accordingly.

10.1.49 CH4_CTRL4 Register (Address = 39h) [reset = 71h]

CH4_CTRL4 is shown in Figure 10-49 and described in Table 10-51.

Return to Summary Table.

Figure 10-49 CH4_CTRL4 Register
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDch4_glitchless_en
R/W-1hR/W-3hR/W-0hR/W-0hR/W-0hR/W-1h
Table 10-51 CH4_CTRL4 Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR/W0h

RESERVED

11-8RESERVEDR/W0h

RESERVED

7-6RESERVEDR/W1h

RESERVED

5-4RESERVEDR/W3h

RESERVED

3-1RESERVEDR/W0h

RESERVED

0ch4_glitchless_enR/W1h

Enables Glitchless switching for Output Channel.

0h = Immediate

1h = Glitchless

10.1.50 CH4_CTRL5 Register (Address = 3Ah) [reset = 8h]

CH4_CTRL5 is shown in Figure 10-50 and described in Table 10-52.

Return to Summary Table.

Figure 10-50 CH4_CTRL5 Register
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDch4_1p8vdetRESERVEDRESERVEDRESERVED
R/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
Table 10-52 CH4_CTRL5 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-4RESERVEDR/W0h

RESERVED.

3ch4_1p8vdetR/W1h

Specify supply on the channel.

0h = 2.5 V or 3.3 V

1h = 1.8 V

2-0RESERVEDR/W0h

RESERVED

10.1.51 CHX_CTRL0 Register (Address = 3Bh) [reset = 61h]

CHX_CTRL0 is shown in Figure 10-51 and described in Table 10-53.

Return to Summary Table.

Figure 10-51 CHX_CTRL0 Register
15141312111098
RESERVEDRESERVEDchx_rstchx_lvds_cmtrim_incchx_lvds_cmtrim_decchx_diffbuf_ibias_trim
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-3h
76543210
chx_diffbuf_ibias_trimchx_lvcmos_drvRESERVEDch0_lvcmos_drvRESERVED
R/W-3hR/W-1hR/W-0hR/W-0hR/W-1h
Table 10-53 CHX_CTRL0 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-14RESERVEDR/W0h

RESERVED

13chx_rstR/W0h

All Channel RST during power up and later. 1h = RST, 0h = Normal.

12-11chx_lvds_cmtrim_incR/W0h

Increments differential output buffer output common-mode programmability.
Use either CHX_LVDS_CMTRIM_INC or CHX_LVDS_CMTRIM_DEC.

10-9chx_lvds_cmtrim_decR/W0h

Decrements differential output buffer output common-mode programmability. Increment
Use either CHX_LVDS_CMTRIM_INC or CHX_LVDS_CMTRIM_DEC.

8-5chx_diffbuf_ibias_trimR/W3h

Differential output buffer tail current programmability.

Ch = 350 µA

8h = 400 µA

4h = 450 µA

0h = 500 µA

0h = 500 µA

1h = 550 µA

2h = 600 µA

3h = 650 µA

4chx_lvcmos_drvR/W1h

Adjust CH1 to CH4 LVCMOS driver strength.

0h = Normal

1h = Fast

3RESERVEDR/W1h

RESERVED

2-1ch0_lvcmos_drvR/W0h

Enable Y0 channel and adjust LVCMOS driver strength.

0h = Off

1h = Normal

3h = Fast

0RESERVEDR/W1h

RESERVED

10.1.52 CHX_CTRL1 Register (Address = 3Ch) [reset = 18h]

CHX_CTRL1 is shown in Figure 10-52 and described in Table 10-54.

Return to Summary Table.

Figure 10-52 CHX_CTRL1 Register
1514131211109876543210
RESERVED
R/W-18h
Table 10-54 CHX_CTRL1 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-0RESERVEDR/W18h

RESERVED

10.1.53 CHX_CTRL2 Register (Address = 3Dh) [reset = 1500h]

CHX_CTRL2 is shown in Figure 10-53 and described in Table 10-55.

Return to Summary Table.

Figure 10-53 CHX_CTRL2 Register
15141312111098
RESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-15h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 10-55 CHX_CTRL2 Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR/W0h

RESERVED

12-8RESERVEDR/W15h

RESERVED

7-0RESERVEDR/W0h

RESERVED

10.1.54 CHX_CTRL3 Register (Address = 3Eh) [reset = 4210h]

CHX_CTRL3 is shown in Figure 10-54 and described in Table 10-56.

Return to Summary Table.

Figure 10-54 CHX_CTRL3 Register
1514131211109876543210
RESERVED
R/W-4210h
Table 10-56 CHX_CTRL3 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-0RESERVEDR/W4210h

RESERVED

10.1.55 CHX_CTRL4 Register (Address = 3Fh) [reset = 210h]

CHX_CTRL4 is shown in Figure 10-55 and described in Table 10-57.

Return to Summary Table.

Figure 10-55 CHX_CTRL4 Register
1514131211109876543210
RESERVED
R/W-210h
Table 10-57 CHX_CTRL4 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-0RESERVEDR/W210h

RESERVED

10.1.56 DBG0 Register (Address = 42h) [reset = 200h]

DBG0 is shown in Figure 10-56 and described in Table 10-58.

Return to Summary Table.

Figure 10-56 DBG0 Register
1514131211109876543210
RESERVED
R/W-200h
Table 10-58 DBG0 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
15-0RESERVEDR/W200h

RESERVED