SCAS886E August   2009  – December 2015 CDCLVP1212

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: LVCMOS Input
    6. 7.6  Electrical Characteristics: Differential Input
    7. 7.7  Electrical Characteristics: LVPECL Output, At VCC = 2.375 V to 2.625 V
    8. 7.8  Electrical Characteristics: LVPECL Output, at VCC = 3.0 V to 3.6 V
    9. 7.9  Pin Characteristics
    10. 7.10 Timing Requirements
    11. 7.11 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Test Configurations
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 LVPECL Output Termination
      2. 9.4.2 Input Termination
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Fanout Buffer for Line Card Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Thermal Management
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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発注情報

9 Detailed Description

9.1 Overview

The CDCLVP1212 uses an open emitter follower stage for its LVPECL outputs. Therefore, proper output biasing and termination are required to ensure correct operation of the device and to maximize output signal integrity. The proper termination for LVPECL outputs is a 50 Ω to (VCC –2) V, but this DC voltage is not readily available on PCB. Therefore, a Thevenin equivalent circuit is worked out for the LVPECL termination in both direct-coupled (DC) and AC-coupled configurations. These configurations are shown in Figure 12 (a and b) for VCC = 2.5 V and Figure 13 (a and b) for VCC = 3.3 V, respectively. It is recommended to place all resistive components close to either the driver end or the receiver end. If the supply voltage for the driver and receiver is different, AC coupling is required.

9.2 Functional Block Diagram

CDCLVP1212 fbd_cas886.gif

9.3 Feature Description

The CDCLVP1212 is a low additive jitter universal to LVPECL fan out buffer with 2 selectable inputs. The small package, low output skew, and low additive jitter make for a flexible device in demanding applications.

9.4 Device Functional Modes

The two inputs of the CDCLVP1212 are internally muxed together and can be selected via the control pin. Unused inputs and outputs can be left floating to reduce overall component cost. Both AC and DC coupling schemes can be used with the CDCLVP1212 to provide greater system flexibility.

9.4.1 LVPECL Output Termination

The CDCLVP1212 is an open emitter for LVPECL outputs. Therefore, proper biasing and termination are required to ensure correct operation of the device and to minimize signal integrity. The proper termination for LVPECL outputs is a 50 Ω to (VCC –2) V, but this DC voltage is not readily available on PCB. Therefore, a Thevenin equivalent circuit is worked out for the LVPECL termination in both direct-coupled (DC) and AC-coupled configurations. These configurations are shown in Figure 12 (a and b) for VCC = 2.5 V and Figure 13 (a and b) for VCC = 3.3 V, respectively. It is recommended to place all resistive components close to either the driver end or the receiver end. If the supply voltage for the driver and receiver is different, AC coupling is required.

CDCLVP1212 ai_lvpecl_dc_ac_out_25_cas886.gif Figure 12. LVPECL Output DC and AC Termination For VCC = 2.5 V
CDCLVP1212 ai_lvpecl_dc_ac_out_33_cas886.gif Figure 13. LVPECL Output DC and AC Termination For VCC = 3.3 V

9.4.2 Input Termination

The CDCLVP1212 inputs can be interfaced with LVPECL, LVDS, or LVCMOS drivers. Figure 14 illustrates how to DC couple an LVCMOS input to the CDCLVP1212. The series resistance (RS) should be placed close to the LVCMOS driver; its value is calculated as the difference between the transmission line impedance and the driver output impedance.

CDCLVP1212 ai_dc_lvcmos_in_cas886.gif Figure 14. DC-Coupled LVCMOS Input to CDCLVP1212

Figure 15 shows how to DC couple LVDS inputs to the CDCLVP1212. Figure 16 and Figure 17 describe the method of DC coupling LVPECL inputs to the CDCLVP1212 for VCC = 2.5 V and VCC = 3.3 V, respectively.

CDCLVP1212 ai_dc_lvds_in_cas886.gif Figure 15. DC-Coupled LVDS Inputs to CDCLVP1212
CDCLVP1212 ai_dc_lvpecl_in_25v_cas886.gif Figure 16. DC-Coupled LVPECL Inputs to CDCLVP1212 (VCC = 2.5 V)
CDCLVP1212 ai_dc_lvpecl_in_33v_cas886.gif Figure 17. DC-Coupled LVPECL Inputs to CDCLVP1212 (VCC = 3.3 V)

Figure 18 and Figure 19 show the technique of AC coupling differential inputs to the CDCLVP1212 for VCC = 2.5–V and VCC = 3.3 V, respectively. It is recommended to place all resistive components close to either the driver end or the receiver end. If the supply voltages of the driver and receiver are different, AC coupling is required.

CDCLVP1212 ai_ac_diff_in_25v_cas886.gif Figure 18. AC-Coupled Differential Inputs to CDCLVP1212 (VCC = 2.5 V)
CDCLVP1212 ai_ac_diff_in_33v_cas886.gif Figure 19. AC-Coupled Differential Inputs to CDCLVP1212 (VCC = 3.3 V)