SCAS886E August   2009  – December 2015 CDCLVP1212

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: LVCMOS Input
    6. 7.6  Electrical Characteristics: Differential Input
    7. 7.7  Electrical Characteristics: LVPECL Output, At VCC = 2.375 V to 2.625 V
    8. 7.8  Electrical Characteristics: LVPECL Output, at VCC = 3.0 V to 3.6 V
    9. 7.9  Pin Characteristics
    10. 7.10 Timing Requirements
    11. 7.11 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Test Configurations
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 LVPECL Output Termination
      2. 9.4.2 Input Termination
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Fanout Buffer for Line Card Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Thermal Management
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Parameter Measurement Information

8.1 Test Configurations

This section describes the function of each block for the CDCLVP1212. Figure 6 through Figure 11 illustrate how the device should be set up for a variety of test configurations.

CDCLVP1212 ai_test_lvpecl_dc_in_cas886.gif Figure 5. DC-Coupled LVPECL Input During Device Test
CDCLVP1212 ai_test_lvcmos_dc_in_cas877.gif Figure 6. DC-Coupled LVCMOS Input During Device Test
CDCLVP1212 ai_vth_var_lvcmos_in_cas877.gif Figure 7. Voltage Variation Over LVCMOS Vth Levels
CDCLVP1212 ai_test_lvds_dc_in_cas886.gif Figure 8. DC-Coupled LVDS Input During Device Test
CDCLVP1212 ai_test_diff_ac_in_cas886.gif Figure 9. AC-Coupled Differential Input To Device
CDCLVP1212 ai_test_lvpecl_dc_out_cas877.gif Figure 10. LVPECL Output DC Configuration During Device Test
CDCLVP1212 ai_test_lvpecl_ac_out_cas877.gif Figure 11. LVPECL Output AC Configuration During Device Test