SLPS405F March   2013  – March 2015 CSD87381P


  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Power Block Performance
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Power Block Characteristics
    7. 5.7 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Power Loss Curves
      2. 6.1.2 Safe Operating Curves (SOA)
      3. 6.1.3 Normalized Curves
      4. 6.1.4 Calculating Power Loss and SOA
        1. Design Example
        2. Calculating Power Loss
        3. Calculating SOA Adjustments
  7. 7Layout
    1. 7.1 Layout Guidelines
      1. 7.1.1 Recommended PCB Design Overview
      2. 7.1.2 Electrical Performance
      3. 7.1.3 Thermal Performance
    2. 7.2 Layout Example
  8. 8Device and Documentation Support
    1. 8.1 Trademarks
    2. 8.2 Electrostatic Discharge Caution
    3. 8.3 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 CSD87381P Package Dimensions
    2. 9.2 Land Pattern Recommendation
    3. 9.3 Stencil Recommendation (100 µm)
    4. 9.4 Stencil Recommendation (125 µm)
    5. 9.5 Pin Drawing
    6. 9.6 CSD87381P Embossed Carrier Tape Dimensions



7 Layout

7.1 Layout Guidelines

7.1.1 Recommended PCB Design Overview

There are two key system-level parameters that can be addressed with a proper PCB design: electrical and thermal performance. Properly optimizing the PCB layout yields maximum performance in both areas. The following provides a brief description on how to address each parameter.

7.1.2 Electrical Performance

The CSD87381P has the ability to switch voltages at rates greater than 10 kV/µs. Take care with the PCB layout design and placement of the input capacitors, inductor, and output capacitors.

  • The placement of the input capacitors relative to VIN and PGND pins of CSD87381P device should have the highest priority during the component placement routine. It is critical to minimize these node lengths. As such, ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 29). The example in Figure 29 uses 1 x 10 nF 0402 25 V and 4 x 10 μF 1206 25 V ceramic capacitors (TDK part number C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the power stage, C21, C5, C8, C19, and C18 should follow in order.
  • The switching node of the output inductor should be placed relatively close to the Power Block II CSD87381P VSW pins. Minimizing the VSW node length between these two components will reduce the PCB conduction losses and actually reduce the switching noise level. See Figure 29. (1)
(1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of Missouri – Rolla

7.1.3 Thermal Performance

The CSD87381P has the ability to utilize the PGND planes as the primary thermal path. As such, the use of thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of solder attach that wicks down the via barrel:

  • Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
  • Use the smallest drill size allowed in your design. The example in Figure 29 uses vias with a 10 mil drill hole and a 16 mil capture pad.
  • Tent the opposite side of the via with solder-mask.

The number and drill size of the thermal vias should align with the end user’s PCB design rules and manufacturing capabilities.

7.2 Layout Example

CSD87381P Thermal_Performance_Image.pngFigure 29. Recommended PCB Layout (Top Down View)