JAJSFP9B July   2018  – June 2021 DAC61416 , DAC71416 , DAC81416

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 8.3.1.1 DAC Transfer Function
        2. 8.3.1.2 DAC Register Structure
          1. 8.3.1.2.1 DAC Register Synchronous and Asynchronous Updates
          2. 8.3.1.2.2 Broadcast DAC Register
          3. 8.3.1.2.3 Clear DAC Operation
      2. 8.3.2 Internal Reference
      3. 8.3.3 Device Reset Options
        1. 8.3.3.1 Power-on-Reset (POR)
        2. 8.3.3.2 Hardware Reset
        3. 8.3.3.3 Software Reset
      4. 8.3.4 Thermal Protection
        1. 8.3.4.1 Analog Temperature Sensor: TEMPOUT Pin
        2. 8.3.4.2 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Toggle Mode
      2. 8.4.2 Differential Mode
      3. 8.4.3 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Stand-Alone Operation
        1. 8.5.1.1 Streaming Mode Operation
      2. 8.5.2 Daisy-Chain Operation
      3. 8.5.3 Frame Error Checking
    6. 8.6 Register Maps
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • RHA|40
サーマルパッド・メカニカル・データ
発注情報

Typical Characteristics

at TA = 25°C, VDD = VAA = 5 V, VREFIN = 2.5 V, unipolar ranges: VSS = 0 V and VCC ≥ VMAX + 1.5 V for the DAC range, bipolar ranges: VSS ≤ VMIN – 1.5 V and VCC ≥ VMAX + 1.5 V for the DAC range, and DAC outputs unloaded (unless otherwise noted)

GUID-4CC0D91C-B211-412E-9105-05767957C96D-low.gif
 
Figure 7-3 Integral Linearity Error vs Digital Input Code (Bipolar Outputs)
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Figure 7-5 Differential Linearity Error vs Digital Input Code (Bipolar Outputs)
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Figure 7-7 Total Unadjusted Error vs Digital Input Code (Bipolar Outputs)
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Figure 7-9 Common Mode Error vs Digital Input Code (Differential Bipolar Outputs)
GUID-EA1A8886-FB66-4AD5-ACA2-7D3610E1A294-low.gif
±20-V output range
Figure 7-11 Integral Linearity Error vs Temperature
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Figure 7-13 Total Unadjusted Error vs Temperature
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Figure 7-15 Unipolar Zero Code Error vs Temperature
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Figure 7-17 Gain Error vs Temperature
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Figure 7-19 Common Mode Error vs Temperature
(Differential Bipolar Outputs)
GUID-B20417A0-6579-417A-99E4-929954E14A74-low.gif
±20-V output range
Figure 7-21 Supply Current (IDD, IAA) vs Digital Input Code
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±20-V output range
Figure 7-23 Supply Current (IIO) vs Supply Voltage
GUID-1D5C251B-7C0A-4A91-9670-B8457AD2E3A5-low.gif
±20-V output range
Figure 7-25 Power-Down Current vs Temperature
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Full-scale code
Figure 7-27 VCC Headroom vs Sourcing Current
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±20-V output range
Figure 7-29 Full-Scale Settling Time, Rising Edge
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Power-down to active DAC mode
±20-V output range
Figure 7-31 DAC Output Enable Glitch
GUID-22BAA8BD-55E8-46AF-B926-3E9936DC2F71-low.gif
±20-V output range
Toggle signal: 1 VPP
DC change: midscale to 3/4 full-scale
Figure 7-33 Toggle Output Change Response
GUID-2B1C89F9-B234-42F0-874E-B8DB9784FEED-low.gifFigure 7-35 Power-Up Response
GUID-06E7F6B4-C7E5-4106-8ED9-8E1ED0BE0456-low.gif
±20-V output range
Full-scale code to 0 V
 
Figure 7-37 Clear Command Response
GUID-6E0FB23D-4CDA-4518-8F3B-1F5548E066BD-low.gif
0 to 5-V output range
Midscale code
Figure 7-39 DAC Output Noise Density vs Frequency
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Figure 7-41 Internal Reference Voltage vs Temperature
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Figure 7-43 Internal Reference Voltage vs Time
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Figure 7-45 Internal Reference Noise
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Figure 7-4 Integral Linearity Error vs Digital Input Code (Unipolar Outputs)
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Figure 7-6 Differential Linearity Error vs Digital Input Code (Unipolar Outputs)
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Figure 7-8 Total Unadjusted Error vs Digital Input Code (Unipolar Outputs)
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Figure 7-10 Common Mode Error vs Digital Input Code (Differential Unipolar Outputs)
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±20-V output range
Figure 7-12 Differential Linearity Error vs Temperature
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Figure 7-14 Unipolar Offset Error vs Temperature
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Figure 7-16 Bipolar Zero Error vs Temperature
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Figure 7-18 Full-Scale Error vs Temperature
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Figure 7-20 Common Mode Error vs Temperature
(Differential Unipolar Outputs)
GUID-16EDD34F-496E-42FE-AC10-E591829A512C-low.gif
±20-V output range
Figure 7-22 Supply Current (ICC, ISS) vs Digital Input Code
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±20-V output range
Figure 7-24 Supply Current vs Temperature
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±20-V output range
Figure 7-26 Source and Sink Capability
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Zero code
Figure 7-28 VSS Footroom vs Sinking Current
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±20-V output range
Figure 7-30 Full-Scale Settling Time, Falling Edge
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0-V to 5-V output range
 
Figure 7-32 Glitch Impulse, 1 LSB Step
GUID-FB5FC671-108B-4E08-A854-347EC24F2135-low.gif
±20-V output range
Toggle signal: 1 VPP
DC value: 3/4 full-scale
Figure 7-34 Toggle Enable Response
GUID-BA4D4DB2-EFC1-4907-9789-1D0AF201CC01-low.gifFigure 7-36 Power-Down Response
GUID-C9354551-17A7-42C2-94D6-7D0E03778697-low.gif
±20-V output range
Toggle signal: 1 VPP
DC value at 20 V
Figure 7-38 Clear Command Response in Toggle Mode
GUID-F9EC4364-4B98-4B76-9761-7A2A67DE7CF0-low.gif
0 to 5-V output range
Midscale code
Figure 7-40 DAC Output Noise
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Figure 7-42 Internal Reference Voltage vs Supply Voltage
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Figure 7-44 Internal Reference Noise Density vs Frequency
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Figure 7-46 Internal Reference Temperature Drift Histogram