JAJSF31B November   2017  – June 2019 DLP3030-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      DLP DLP3030-Q1のブロック・システム図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Physical Characteristics of the Micromirror Array
    11. 6.11 Optical Characteristics of the Micromirror Array
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Micromirror Array
      2. 7.3.2 Double Data Rate (DDR) Interface
      3. 7.3.3 Micromirror Switching Control
      4. 7.3.4 DMD Voltage Supplies
      5. 7.3.5 Logic Reset
      6. 7.3.6 Temperature Sensing Diode
        1. 7.3.6.1 Temperature Sense Diode Theory
      7. 7.3.7 Active Array Temperature
      8. 7.3.8 DMD JTAG Interface
    4. 7.4 Optical Performance
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill and Alignment
    5. 7.5 DMD Image Quality Specification
    6. 7.6 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 HUD Reference Design and LED Controller Reference Design
    3. 8.3 Application Mission Profile Consideration
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Sequencing Requirements
      1. 9.1.1 Power Up and Power Down
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Temperature Diode Pins
    3. 10.3 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デバイスの項目表記
      2. 11.1.2 デバイスのマーキング
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 デバイスの取り扱い
    8. 11.8 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
SUPPLY VOLTAGE RANGE
VREF LVCMOS interface power supply voltage(3) 1.65 1.8 1.95 V
VCC LVCMOS logic power supply voltage(3) 2.25 2.5 2.75 V
VOFFSET Mirror electrode and HVCMOS voltage(3) 8.25 8.5 8.75 V
VBIAS Mirror electrode voltage 15.5 16 16.5 V
|VBIAS – VOFFSET| Supply voltage delta(2) 8.75 V
VRESET Mirror electrode voltage –9.5 –10 –10.5 V
VP  VT+ Positive going threshold voltage 0.4 × VREF 0.7 × VREF V
VN  VT– Negative going threshold voltage  0.3 × VREF 0.6 × VREF V
VH  ∆VT Hysteresis voltage (Vp – Vn) 0.1 × VREF 0.4 × VREF V
IOH_TDO High level output current @ Voh = 2.25 V, TDO, Vcc = 2.25 V –2 mA
IOL_TDO Low level output current  @ Vol = 0.4 V, TDO, Vcc = 2.25 V 2 mA
TEMPERATURE DIODE
ITEMP_DIODE Max current source into temperature diode(5) 120 µA
ENVIRONMENTAL
ILLUV(4) Illumination, wavelength < 395 nm 0.68 2.0 mW/cm2
ILLIR Illumination, wavelength > 800 nm 10 mW/cm2
TARRAY Operating DMD array temperature (monitored by TMP411-Q1 via DLPC120-Q1)(1)(6)(7) –40 105 °C
ILLOVERFILL(8) Illumination overfill maximum allowable heat load on left and bottom sides of the aperture, TARRAY < 75°C(9) 26 mW/mm2
Illumination overfill maximum allowable heat load on left and bottom sides of the aperture, TARRAY > 75°C(9) 20 mW/mm2
(1) DMD active array temperature can be calculated as shown in Active Array Temperature section. Additionally, the DMD array temperature is monitored in the system using the TMP411-Q1 and DLPC120-Q1 as shown in the system block diagram.
(2) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than or equal to 8.75 V.
(3) VBIAS, VCC, VOFFSET, VREF, VRESET, VSS are required to operate the DMD.
(4) The maximum operation conditions for operating temperature and illumination UV shall not be implemented simultaneously.
(5) Temperature Diode is to allow accurate measurement of the DMD array temperature during operation.
(6) For applications that are higher brightness (> 1000 lumens) or underfill the active array optically, the TMP411-Q1 and temperature sensing diode are not sufficient to determine maximum array temperature. Contact TI Applications Engineering for array temperature calculation methods for this application.
(7) TI assumes a normal automotive operating profile without continuous operation at either minimum or maximum temperatures. Operating profile information for device duty cycle and temperature may be provided if requested.
(9) Heat load outside the aperture in the red areas shown in the figure below should not exceed the values listed in the table. These values assume a uniform distribution. For a non-uniform distribution, please contact TI Applications Engineering for additional information.
DLP3030-Q1 DS-s450AutoG15-Ap-illum.gif