JAJSK35B September   2020  – May 2022 DLP471NE

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Temperature Sensor Diode
  9. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Impedance Requirements
    3. 10.3 Layers
    4. 10.4 Trace Width, Spacing
    5. 10.5 Power
    6. 10.6 Trace Length Matching Recommendations
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
      2. 11.2.2 Device Markings
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-B8F060C1-51F7-455C-A14B-8F98EBBA1EB2-low.gifFigure 5-1 FYN Package149-Pin PGABottom View
CAUTION:

Properly manage the layout and the operation of signals identified in the Pin Functions table to make sure there is reliable, long-term operation of the 0.47” Full HD S451 DMD. Refer to the PCB Design Requirements for TI DLP TRP Digital Micromirror Devices application report for specific details and guidelines before designing the board.

Table 5-1 Pin Functions
PIN INPUT-OUTPUT(1) DESCRIPTION TRACE LENGTH (mm)
NAME No.
D_AP(0) J1 I High–speed differential data pair lane A0 16.24427
D_AN(0) H1 I High–speed differential data pair lane A0 16.24426
D_AP(1) G1 I High–speed differential data pair lane A1 16.39699
D_AN(1) F1 I High–speed differential data pair lane A1 16.39691
D_AP(2) F2 I High–speed differential data pair lane A2 15.58905
D_AN(2) E2 I High–speed differential data pair lane A2 15.58908
D_AP(3) D2 I High–speed differential data pair lane A3 14.98471
D_AN(3) C2 I High–speed differential data pair lane A3 14.9844
D_AP(4) A3 I High–speed differential data pair lane A4 12.89101
D_AN(4) A4 I High–speed differential data pair lane A4 12.89101
D_AP(5) A5 I High–speed differential data pair lane A5 10.57206
D_AN(5) A6 I High–speed differential data pair lane A5 10.57242
D_AP(6) A7 I High–speed differential data pair lane A6 8.48593
D_AN(6) A8 I High–speed differential data pair lane A6 8.48702
D_AP(7) A9 I High–speed differential data pair lane A7 6.63434
D_AN(7) A10 I High–speed differential data pair lane A7 6.63441
DCLK_AP C1 I High–speed differential clock A 15.53899
DCLK_AN D1 I High–speed differential clock A 15.53868
D_BP(0) A11 I High–speed differential data pair lane B0 4.52398
D_BN(0) A12 I High–speed differential data pair lane B0 4.52368
D_BP(1) A13 I High–speed differential data pair lane B1 6.4103
D_BN(1) A14 I High–speed differential data pair lane B1 6.40894
D_BP(2) A15 I High–speed differential data pair lane B2 8.78102
D_BN(2) A16 I High–speed differential data pair lane B2 8.78364
D_BP(3) A18 I High–speed differential data pair lane B3 12.05827
D_BN(3) A19 I High–speed differential data pair lane B3 12.06154
D_BP(4) D19 I High–speed differential data pair lane B4 11.04817
D_BN(4) C19 I High–speed differential data pair lane B4 11.0479
D_BP(5) H20 I High–speed differential data pair lane B5 14.54976
D_BN(5) J20 I High–speed differential data pair lane B5 14.54991
D_BP(6) D20 I High–speed differential data pair lane B6 11.67363
D_BN(6) E20 I High–speed differential data pair lane B6 11.67598
D_BP(7) F20 I High–speed differential data pair lane B7 12.33442
D_BN(7) G20 I High–speed differential data pair lane B7 12.33409
DCLK_BP B17 I High–speed differential clock B 10.22973
DCLK_BN B18 I High–speed differential clock B 10.22551
LS_WDATA_P T10 I LVDS data 7.8047
LS_WDATA_N R11 I LVDS data 0.64391
LS_CLK_P R9 I LVDS CLK 8.20952
LS_CLK_N R10 I LVDS CLK 7.35885
LS_RDATA_A_BISTA T13 O LVCMOS output 2.01174
BIST_B T12 O LVCMOS output 2.20006
AMUX_OUT B20 O Analog test mux 10.74435
DMUX_OUT R14 O Digital test mux 2.25459
DMD_DEN_ARSTZ T11 I ARSTZ 2.00365
TEMP_N R8 I Temp diode N 9.03231
TEMP_P R7 I Temp diode P 11.38391
VDD B13, B7, C18, E3, H3, J2, K3, L2, L19, M1, M2, N3, N19, P2, P18, R3, R5, R12, R17, R19, T2, T4, T6, T8, T18 P Digital core supply voltage Plane
VDDA B11, B16, B4, B9, C20, D3, E18, G2, G19 P HSSI supply voltage Plane
VRESET B3, R1 P Supply voltage for negative bias of micromirror reset signal Plane
VBIAS E1, P1 P Supply voltage for positive bias of micromirror reset signal Plane
VOFFSET A20, B2, T1, T20 P Supply voltage for HVCMOS logic, stepped up logic level Plane
VSS A17, B10, B14, B6, D18, F3, F19, J3, K19, K2, L1, L3, M3, N2, N18, N20, P3, P20, R2, R4, R6, R13, R20, T5, T7, T16, T17, T19 G Ground Plane
VSSA B12, B15, B19, B5, B8, C3, E19, G3, H2, H19, K1, N1, P19, R18, T3, T9 G Ground Plane
N/C F18, G18, H18, J18, J19, K18, K20, L18, L20, M18, M19, M20, R15, R16, T14, T15 No connect
(1) I=Input, O=output, P=Power, G=Ground, NC = No Connect