JAJSQ48 april   2023 DLP550HE

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 説明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Capacitance at Recommended Operating Conditions
    8. 6.8  Timing Requirements
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  10. 9 Power Supply Recommendations
    1. 9.1 DMD Power Supply Power-Up Procedure
    2. 9.2 DMD Power Supply Power-Down Procedure
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Layers
      2. 10.2.2 Impedance Requirements
      3. 10.2.3 Trace Width, Spacing
  12. 11Device and Documentation Support
    1. 11.1 サード・パーティ製品に関する免責事項
    2. 11.2 Device Support
      1. 11.2.1 Device Nomenclature
      2. 11.2.2 Device Markings
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.8 Timing Requirements

Over Section 6.4 (unless otherwise noted).
PARAMETER DESCRIPTION SIGNAL MIN TYP MAX UNIT
LVDS(1)
tC Clock Cycle DCLK_A LVDS 4.34 5 ns
tC Clock Cycle DCLK_B LVDS 4.34 5 ns
tW Pulse Width DCLK_A LVDS 2.17 2.5 ns
tW Pulse Width DCLK_B LVDS 2.17 2.5 ns
tSU Setup Time D_A(15:0) before DCLK_A LVDS 0.35 ns
tSU Setup Time D_A(15:0) before DCLK_B LVDS 0.35 ns
tSU Setup Time SCTRL_A before DCLK_A LVDS 0.35 ns
tSU Setup Time SCTRL_B before DCLK_B LVDS 0.35 ns
tH Hold Time D_A(15:0) after DCLK_A LVDS 0.65 ns
tH Hold Time D_B(15:0) after DCLK_B LVDS 0.65 ns
tH Hold Time SCTRL_A after DCLK_A LVDS 0.65 ns
tH Hold Time SCTRL_B after DCLK_B LVDS 0.65 ns
tSKEW Skew Time Channel B relative to Channel A(2)(3) LVDS –1.25 1.25 ns
(1) See Figure 6-6 for timing requirements for LVDS.
(2) Channel A (Bus A) includes the following LVDS pairs: DCLK_AN and DCLK_AP, SCTRL_AN and SCTRL_AP, D_AN(15:0) and D_AP(15:0).
(3) Channel B (Bus B) includes the following LVDS pairs: DCLK_BN and DCLK_BP, SCTRL_BN and SCTRL_BP, D_BN(15:0) and D_BP(15:0).
GUID-6D25CD48-FEC2-4EB3-9328-A15C10DA2759-low.gif Figure 6-2 SCP Timing Requirements

See Section 6.4 for fSCPCLK, tSCP_DS, tSCP_DH, and tSCP_PD specifications.

See Section 6.4 for tr and tf specifications and conditions.

GUID-0F81250E-6141-4BEF-8C32-EDA8E907650D-low.gif
Not to scale.
Refer to the Section 6.8.
Refer to Section 5 for list of LVDS pins and SCP pins.
Figure 6-3 Rise Time and Fall Time
GUID-C9249BCC-EB48-4A6F-8946-F99285B32E54-low.gif Figure 6-4 Test Load Circuit for Output Propagation Measurement

For output timing analysis, the tester pin electronics and its transmission line effects must be considered. System designers must use IBIS or other simulation tools to correlate the timing reference load to a system environment. See Figure 6-4.

GUID-543C6E0C-EB85-4F65-9CF2-EF3938812252-low.gif Figure 6-5 LVDS Waveform Requirements

See Section 6.4 for VCM, VID, and VLVDS specifications and conditions.

GUID-E5E3657E-6C4F-4F01-B8D7-9419F2523270-low.gif Figure 6-6 Timing Requirements

See Section 6.8 for timing requirements and LVDS pairs per channel (bus) defining D_P(0:x) and D_N(0:x).