JAJSQ48 データシート

JAJSQ48 april 2023 DLP550HE

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

FYA|149
- MCLG018B

サーマルパッド・メカニカル・データ

発注情報

jajsq48_oa

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by this table. No level of performance is implied when operating the device above or below these limits.

		MIN	NOM	MAX	UNIT
VOLTAGE SUPPLY
V_CC	Supply voltage for LVCMOS core logic⁽¹⁾	3.0	3.3	3.6	V
V_CCI	Supply voltage for LVDS interface⁽¹⁾⁽²⁾	3.0	3.3	3.6	V
V_CC2	Micromirror electrode and HVCMOS voltage⁽¹⁾	7.25	7.5	7.75	V
V_MBRST	Micromirror bias / reset voltage	–27		26.5	V
LVCMOS INTERFACE
V_IH	Input high voltage⁽³⁾	1.7	2.5	V_CC + 0.3	V
V_IL	Input low voltage⁽³⁾	–0.3		0.7	V
I_OH	High level output current			–30	mA
I_OL	Low level output current			25	mA
t_PWRDNZ	PWRDNZ pulse width⁽⁴⁾	10			ns
SCP INTERFACE
ƒ_SCPCLK	SCP clock frequency⁽⁵⁾	50		500	kHz
t_{SCP_SKEW}	Time between valid SCPDI and rising-edge of SCPCLK⁽⁶⁾	-300		300	ns
t_{SCP_DELAY}	Time between valid SCPDO and rising-edge of SCPCLK⁽⁶⁾			960	ns
t_{SCP_NEG_ENZ}	Time between falling-edge of SCPENZ and the rising-edge of SCPCLK.⁽⁵⁾	6/ƒ_DCLK			s
t_{SCP_OUT_EN}	Time required for SCP output buffer to recover after SCPENZ (from tristate)			192/ƒ_DCLK	s
t_{SCP_PW_ENZ}	SCPENZ inactive pulse width (high level)	1			1/ƒ_scpclk
t_r	Rise Time (20% to 80%)⁽⁶⁾			200	ns
t_f	Fall time (80% to 20%)⁽⁶⁾			200	ns
LVDS INTERFACE
ƒ_CLOCK	Clock frequency for LVDS interface, DCLK_A and DCLK_B⁽⁷⁾		200	230	MHz
\|V_ID\|	Input differential voltage (absolute value)⁽⁷⁾	100	400	600	mV
V_CM	Common mode voltage⁽⁷⁾		1200		mV
V_LVDS	LVDS voltage⁽⁷⁾	0		1900	mV
t_r	Rise Time (20% to 80%)⁽⁸⁾	100		400	ns
t_f	Fall time (80% to 20%)⁽⁸⁾	100		400	ns
t_{LVDS_RSTZ}	Time required for LVDS receivers to recover from PWRDNZ			10	ns
Z_IN	Internal differential termination resistance	95		105	Ω
Z_LINE	Line differential impedance (PWB/trace)	85	90	95	Ω
ENVIRONMENT
T_ARRAY	Array temperature, long-term operational⁽⁹⁾⁽¹⁰⁾⁽¹¹⁾⁽¹²⁾⁽¹³⁾	10		40 to 70	°C
T_ARRAY	Array temperature, short-term operational, 500-hr max⁽¹⁰⁾⁽¹⁴⁾	0		10	°C
T_WINDOW	Window temperature, operational⁽¹⁵⁾			85	°C
\|T_DELTA\|	Absolute Temperature delta between any point on the window edge and the ceramic test point TP1⁽¹⁶⁾			14	°C
T_DP-AVG	Average dew point temperature (non-condensing)⁽¹⁷⁾			28	°C
T_DP-ELR	Elevated dew point temperature range (non-condensing)⁽¹⁸⁾	28		36	°C
CT_ELR	Cumulative time in elevated dew point temperature range			24	months
LAMP ILLUMINATION
ILL_UV	Illumination Wavelengths < 395 nm⁽⁹⁾		0.68	2	mW/cm²
ILL_VIS	Illumination Wavelengths between 395 nm and 800 nm⁽¹³⁾	Thermally limited			W/cm²
ILL_IR	Illumination Wavelengths > 800 nm			10	mW/cm²
SOLID STATE ILLUMINATION
ILL_UV	Illumination Wavelengths < 410 nm⁽⁹⁾			3	mW/cm²
ILL_VIS	Illumination Wavelengths between 410 nm and 800 nm⁽¹³⁾	Thermally limited			W/cm²
ILL_IR	Illumination Wavelengths > 800 nm			10	mW/cm²

(1) All voltages are referenced to common ground V_SS. V_CC, V_CCI, and V_CC2 power supplies are all required for proper DMD operation. V_SS (GND) must also be connected.

(2) To prevent excess current, the supply voltage delta |V_CCI – V_CC| must be less than the specified limit. See Section 9, Figure 9-1, and Figure 9-1.

(3) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, “Low-Power Double Data Rate (LPDDR)” JESD209B. Tester Conditions for V_IH and V_IL.

Frequency = 60 MHz. Maximum Rise Time = 2.5 ns @ (20% to 80%).
Frequency = 60 MHz. Maximum Fall Time = 2.5 ns @ (80% to 20%).

(4) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tristates the SCPDO output pin.

(5) The SCP clock is a gated clock. Duty cycle must be 50% ± 10%. SCP parameter is related to the frequency of DCLK.

(6) See Figure 6-2.

(7) See LVDS Timing Requirements in Section 6.8 and Figure 6-6.

(8) See Figure 6-5 LVDS Waveform Requirements.

(9) Simultaneous exposure of the DMD to the maximum Section 6.4 for temperature and UV illumination reduces device lifetime.

(10) The array temperature cannot be measured directly and must be computed analytically from the temperature measure at test point (TP1) shown in Figure 7-1 and the Thermal Table using the Section 7.6.

(11) Per Figure 6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to Section 7.7 for a definition of micromirror landed duty cycle.

(12) Long-term is defined as the usable life of the device.

(13) The maximum optical power that can be incident on the DMD is limited by the maximum optical power density and the micromirror array temperature.

(14) Short-term is the total cumulative time over the useful life of the device.

(15) The locations of thermal test points TP2, TP3, TP4, and TP5 shown in Figure 7-1 are intended to measure the highest window edge temperature. For most applications, the locations shown are representative of the highest window edge temperature. If a particular application causes additional points on the window edge to be at a higher temperature, test points should be added to those locations.

(16) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in Figure 7-1. The window test points TP2, TP3, TP4, and TP5 shown in Figure 7-1 are intended to result in the worst case delta temperature. If a particular application causes another point on the window edge to result in a larger delta in temperature, that point should be used.

(17) The average over time (including storage and operating) that the device is not in the 'elevated dew point temperature range'.

(18) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative time of CT_ELR.

Figure 6-1 Max Recommended Array Temperature—Derating Curve