During power-down,
VCC and VCCI must be supplied until
after VCC2 is discharged to within the specified limit of ground.
Refer to Section 6.4.
Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the requirements listed in Section 6.1 and in Section 6.4. During power-down, LVCMOS input pins must be less than specified in Section 6.4.
Figure 9-1 Power Supply Timing
A. See Pin Configuration and Functions for pin functions.
B. VCC must be up and stable prior to VCC2 powering up.
C. PWRDNZ has two turn on options. Option 1: PWRDNZ does not go high until VCC and VCC2 are up and stable, or Option 2: PWRDNZ must be pulsed low for a minimum of TPWRDNZ, or 10 ns after VCC and VCC2 are up and stable.
D. There is a minimum of TLVDS_ARSTZ, or 2 μs, wait time from PWRDNZ going high for the LVDS receiver to recover.
E. After the DMD micromirror park sequence is complete, the DLP controller software initiates a hardware power-down that activates the PWRDNZ and disables VCC2.
F. Under power-loss conditions, where emergency DMD micromirror park procedures are being enacted by the DLP controller hardware, PWRDNZ goes low.
G. VCC must remain high until after VCC2 goes low.
H. To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit in Section 6.4.