DLPS031C December   2013  – August 2015 DLPC6401

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics (Normal Mode)
    7. 6.7  System Oscillators Timing Requirements
    8. 6.8  Test and Reset Timing Requirements
    9. 6.9  JTAG Interface: I/O Boundary Scan Application Timing Requirements
    10. 6.10 Port 1 Input Pixel Interface Timing Requirements
    11. 6.11 Port 2 Input Pixel Interface (FPD-Link Compatible LVDS Input) Timing Requirements
    12. 6.12 Synchronous Serial Port (SSP) Interface Timing Requirements
    13. 6.13 Programmable Output Clocks Switching Characteristics
    14. 6.14 Synchronous Serial Port (SSP) Interface Switching Characteristics
    15. 6.15 JTAG Interface: I/O Boundary Scan Application Switching Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 System Reset Operation
        1. 7.3.1.1 Power-Up Reset Operation
        2. 7.3.1.2 System Reset Operation
        3. 7.3.1.3 Spread Spectrum Clock Generator Support
        4. 7.3.1.4 GPIO Interface
        5. 7.3.1.5 Source Input Blanking
        6. 7.3.1.6 Video and Graphics Processing Delay
      2. 7.3.2 Program Memory Flash/SRAM Interface
        1. 7.3.2.1 Calibration and Debug Support
        2. 7.3.2.2 Board-Level Test Support
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Recommended MOSC Crystal Oscillator Configuration
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 System Power Regulation
    2. 9.2 System Power-Up Sequence
    3. 9.3 Power-On Sense (POSENSE) Support
    4. 9.4 System Environment and Defaults
      1. 9.4.1 DLPC6401 System Power-Up and Reset Default Conditions
      2. 9.4.2 1.2-V System Power
      3. 9.4.3 1.8-V System Power
      4. 9.4.4 1.9-V System Power
      5. 9.4.5 3.3-V System Power
      6. 9.4.6 FPD-Link Input LVDS System Power
      7. 9.4.7 Power Good (PWRGOOD) Support
      8. 9.4.8 5-V Tolerant Support
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Layout Guidelines for Internal ASIC Power
      2. 10.1.2 PCB Layout Guidelines for Quality Auto-Lock Performance
      3. 10.1.3 DMD Interface Considerations
      4. 10.1.4 General Handling Guidelines for Unused CMOS-Type Pins
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1 Video Timing Parameter Definitions
        2. 11.1.1.2 Device Marking
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

7.3 Feature Description

Table 2. (LVDS) Receiver Supported Pixel Mapping Modes(1)

LVDS RECEIVER INPUT MAPPING SELECTION 1 MAPPING SELECTION 2 MAPPING SELECTION 3 MAPPING SELECTION 4(2) [18-Bit Mode]
RA Input Channel
RDA(6) Map to GRN(4) Map to GRN(2) Map to GRN(0) Map to GRN(4)
RDA(5) Map to RED(9) Map to RED(7) Map to RED(5) Map to RED(9)
RDA(4) Map to RED(8) Map to RED(6) Map to RED(4) Map to RED(8)
RDA(3) Map to RED(7) Map to RED(5) Map to RED(3) Map to RED(7)
RDA(2) Map to RED(6) Map to RED(4) Map to RED(2) Map to RED(6)
RDA(1) Map to RED(5) Map to RED(3) Map to RED(1) Map to RED(5)
RDA(0) Map to RED(4) Map to RED(2) Map to RED(0) Map to RED(4)
RB Input Channel
RDB(6) Map to BLU(5) Map to BLU(3) Map to BLU(1) Map to BLU(5)
RDB(5) Map to BLU(4) Map to BLU(2) Map to BLU(0) Map to BLU(4)
RDB(4) Map to GRN(9) Map to GRN(7) Map to GRN(5) Map to GRN(9)
RDB(3) Map to GRN(8) Map to GRN(6) Map to GRN(4) Map to GRN(8)
RDB(2) Map to GRN(7) Map to GRN(5) Map to GRN(3) Map to GRN(7)
RDB(1) Map to GRN(6) Map to GRN(4) Map to GRN(2) Map to GRN(6)
RDB(0) Map to GRN(5) Map to GRN(3) Map to GRN(1) Map to GRN(5)
RC Input Channel
RDC(6) Map to DEN
RDC(5) Map to VSYNC
RDC(4) Map to HSYNC
RDC(3) Map to BLU(9) Map to BLU(7) Map to BLU(5) Map to BLU(9)
RDC(2) Map to BLU(8) Map to BLU(6) Map to BLU(4) Map to BLU(8)
RDC(1) Map to BLU(7) Map to BLU(5) Map to BLU(3) Map to BLU(7)
RDC(0) Map to BLU(6) Map to BLU(4) Map to BLU(2) Map to BLU(6)
RD Input Channel
RDD(6) Map to field (option 1 if applicable)
RDD(5) Map to BLU(3) Map to BLU(9) Map to BLU(7) No mapping
RDD(4) Map to BLU(2) Map to BLU(8) Map to BLU(6) No mapping
RDD(3) Map to GRN(3) Map to GRN(9) Map to GRN(7) No mapping
RDD(2) Map to GRN(2) Map to GRN(8) Map to GRN(6) No mapping
RDD(1) Map to RED(3) Map to RED(9) Map to RED(7) No mapping
RDD(0) Map to RED(2) Map to RED(8) Map to RED(6) No mapping
RE Input Channel
RDE(6) Map to field (option 2 if applicable)
RDE(5) Map to BLU(1) Map to BLU(9) No mapping
RDE(4) Map to BLU(0) Map to BLU(8) No mapping
RDE(3) Map to GRN(1) Map to GRN(9) No mapping
RDE(2) Map to GRN(0) Map to GRN(8) No mapping
RDE(1) Map to RED(1) Map to RED(9) No mapping
RDE(0) Map to RED(0) Map to RED(8) No mapping
(1) Mapping options are selected by software.
(2) If mapping option 4 is the only mapping mode needed, and if, and only if, a 'Field 1' or 'Field 2' input is not needed, then the board layout can leave the LVDS inputs for RD and RE channels floating.