PHYCR is shown in Table 47.
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|15||Auto MDI/X Enable||R/W,STRAP||0x1||
Auto-MDIX Enable: BASIC Mode: Default to A-MDIX enabled. ENHANCED Mode : Latched by strap A-MDIX
0x0 = Disable Auto-Negotiation Auto-MDIX capability
0x1 = Enable Auto-Negotiation Auto-MDIX capability
Force MDIX: ENHANCED Mode: When A-MDIX strap is disabled, latched by FORCE MDI/MDIX strap
0x0 = Normal operation (Receive on RD pair, Transmit on TD pair)
0x1 = Force MDI pairs to cross (Receive on TD pair, Transmit on RD pair)
|13||Pause RX Status||R||0x0||
Pause Receive Negotiation Status: Indicates that pause receive should be enabled in the MAC. Based on bits [11:10] in ANAR register and bits [11:10] in ANLPAR register settings. The function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, 'Pause Resolution', only if the Auto-Negotiation highest common denominator is a Full-Duplex technology.
|12||Pause TX Status||R||0x0||
Pause Transmit Negotiated Status: Indicates that pause should be enabled in the MAC. Based on bits [11:10] in ANAR register and bits [11:10] in ANLPAR register settings. This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, 'Pause Resolution', only if the Auto-Negotiation highest common denominator is a Full-Duplex technology.
|11||MII Link Status||R||0x0||
MII Link Status:
0x0 = No active 100Base-TX Full-Duplex link, established using Auto-Negotiation
0x1 = 100Base-TX Full-Duplex link is active and it was established using Auto-Negotiation
|7||Bypass LED Stretching||R/W||0x0||
Bypass LED Stretching: Set this bit to '1' to bypass the LED stretching, the LED reflects the internal value.
0x0 = Normal LED operation
0x1 = Bypass LED stretching
PHY Address: BASIC Mode: Latched by Strap ENHANCED Mode: Latched by Strap