JAJSHP7D May   2015  – July 2019 DRV8305-Q1

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      概略回路図
  4. 改訂履歴
  5. 概要(続き)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Timing Requirements (Slave Mode Only)
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Integrated Three-Phase Gate Driver
      2. 8.3.2 INHx/INLx: Gate Driver Input Modes
      3. 8.3.3 VCPH Charge Pump: High-Side Gate Supply
      4. 8.3.4 VCP_LSD LDO: Low-Side Gate Supply
      5. 8.3.5 GHx/GLx: Half-Bridge Gate Drivers
        1. 8.3.5.1 Smart Gate Drive Architecture: IDRIVE
        2. 8.3.5.2 Smart Gate Drive Architecture: TDRIVE
        3. 8.3.5.3 CSAs: Current Shunt Amplifiers
      6. 8.3.6 DVDD and AVDD: Internal Voltage Regulators
      7. 8.3.7 VREG: Voltage Regulator Output
      8. 8.3.8 Protection Features
        1. 8.3.8.1 Fault and Warning Classification
        2. 8.3.8.2 MOSFET Shoot-Through Protection (TDRIVE)
        3. 8.3.8.3 MOSFET Overcurrent Protection (VDS_OCP)
          1. 8.3.8.3.1 MOSFET dV/dt Turn On Protection (TDRIVE)
          2. 8.3.8.3.2 MOSFET Gate Drive Protection (GDF)
        4. 8.3.8.4 Low-Side Source Monitors (SNS_OCP)
        5. 8.3.8.5 Fault and Warning Operating Modes
      9. 8.3.9 Undervoltage Warning (UVFL), Undervoltage Lockout (UVLO), and Overvoltage (OV) Protection
        1. 8.3.9.1 Overtemperature Warning (OTW) and Shutdown (OTSD) Protection
        2. 8.3.9.2 Reverse Supply Protection
        3. 8.3.9.3 MCU Watchdog
        4. 8.3.9.4 VREG Undervoltage (VREG_UV)
        5. 8.3.9.5 Latched Fault Reset Methods
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Up Sequence
      2. 8.4.2 Standby State
      3. 8.4.3 Operating State
      4. 8.4.4 Sleep State
      5. 8.4.5 Limp Home or Fail Code Operation
    5. 8.5 Programming
      1. 8.5.1 SPI Communication
        1. 8.5.1.1 SPI
        2. 8.5.1.2 SPI Format
    6. 8.6 Register Maps
      1. 8.6.1 Status Registers
        1. 8.6.1.1 Warning and Watchdog Reset (Address = 0x1)
          1. Table 10. Warning and Watchdog Reset Register Description
        2. 8.6.1.2 OV/VDS Faults (Address = 0x2)
          1. Table 11. OV/VDS Faults Register Description
        3. 8.6.1.3 IC Faults (Address = 0x3)
          1. Table 12. IC Faults Register Description
        4. 8.6.1.4 VGS Faults (Address = 0x4)
          1. Table 13. Gate Driver VGS Faults Register Description
      2. 8.6.2 Control Registers
        1. 8.6.2.1 HS Gate Drive Control (Address = 0x5)
          1. Table 14. HS Gate Driver Control Register Description
        2. 8.6.2.2 LS Gate Drive Control (Address = 0x6)
          1. Table 15. LS Gate Driver Control Register Description
        3. 8.6.2.3 Gate Drive Control (Address = 0x7)
          1. Table 16. Gate Drive Control Register Description
        4. 8.6.2.4 IC Operation (Address = 0x9)
          1. Table 17. IC Operation Register Description
        5. 8.6.2.5 Shunt Amplifier Control (Address = 0xA)
          1. Table 18. Shunt Amplifier Control Register Description
        6. 8.6.2.6 Voltage Regulator Control (Address = 0xB)
          1. Table 19. Voltage Regulator Control Register Description
        7. 8.6.2.7 VDS Sense Control (Address = 0xC)
          1. Table 20. VDS Sense Control Register Description
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Gate Drive Average Current
        2. 9.2.2.2 MOSFET Slew Rates
        3. 9.2.2.3 Overcurrent Protection
        4. 9.2.2.4 Current Sense Amplifiers
      3. 9.2.3 VREG Reference Voltage Input (DRV8305N)
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Consideration in Generator Mode
    2. 10.2 Bulk Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

INHx/INLx: Gate Driver Input Modes

The DRV8305-Q1 can be operated in three different inputs modes to support various commutation schemes.

  • Table 2 shows the truth table for the 6-PWM input mode. This mode allows for each half-bridge to be placed in one of three states, either High, Low, or Hi-Z, based on the inputs.
  • Table 2. 6-PWM Truth Table

    INHx INLx GHx GLx
    1 1 L L
    1 0 H L
    0 1 L H
    0 0 L L
    DRV8305-Q1 6_PWM_mode_slvsd12.gifFigure 6. 6-PWM Mode
  • Table 3 shows the truth table for the 3-PWM input mode. This mode allows for each half-bridge to be placed in one of two states, either High or Low, based on the inputs. The three high-side inputs (INHx) are used to control the state of the half-bridge with the complimentary low-side signals being generated internally. Dead time can be adjusted through the internal setting (DEAD_TIME) in the SPI registers. In this mode all activity on INLx is ignored.
  • Table 3. 3-PWM Truth Table

    INHx INLx GHx GLx
    1 X H L
    0 X L H
    DRV8305-Q1 3_PWM_mode_slvsd12.gifFigure 7. 3-PWM Mode
  • Table 4 and Table 5 show the truth tables for the 1-PWM input mode. The 1-PWM mode uses an internally stored 6-step block commutation table to control the outputs of the three half-bridge drivers based on one PWM and three GPIO inputs. This mode allows the use of a lower cost microcontroller by requiring only one PWM resource. The PWM signal is applied on pin INHA (PWM_IN) to set the duty cycle of the half-bridge outputs along with the three GPIO signals on pins INLA (PHC_0), INHB (PHC_1), INLB (PHC_2) that serve to set the value of a three bit register for the commutation table. The PWM may be operated from 0-100% duty cycle. The three bit register is used to select the state for each half-bridge for a total of eight states including an align and stop state.
  • An additional and optional GPIO, INHC (DWELL) can be used to facilitate the insertion of dwell states or phase current overlap states between the six commutation steps. This may be used to reduce acoustic noise and improve motion through the reduction of abrupt current direction changes when switching between states. INHC must be high when the state is changed and the dwell state will exist until INHC is taken low. If the dwell states are not being used, the INHC pin can be tied low.

    In 1-PWM mode all activity on INLC is ignored.

    DRV8305-Q1 1_PWM_mode_slvsd12.gifFigure 8. 1-PWM Mode

    The method of freewheeling can be selected through an SPI register (COMM_OPTION). Diode freewheeling is when the phase current is carried by the body diode of the external power MOSFET during periods when the MOSFET is reverse biased (current moving from source to drain). In active freewheeling, the power MOSFET is enabled during periods when the MOSFET is reverse biased. This allows the system to improve efficiency due to the typically lower impedance of the MOSFET conduction channel as compared to the body diode. Table 4 shows the truth table for active freewheeling. Table 5) shows the truth table for diode freewheeling.

Table 4. 1-PWM Active Freewheeling

STATE INLA:INHB:INLB:INHC GHA GLA GHB GLB GHC GLC
AB 0110 PWM !PWM LOW HIGH LOW LOW
AB_CB 0101 PWM !PWM LOW HIGH PWM !PWM
CB 0100 LOW LOW LOW HIGH PWM !PWM
CB_CA 1101 LOW HIGH LOW HIGH PWM !PWM
CA 1100 LOW HIGH LOW LOW PWM !PWM
CA_BA 1001 LOW HIGH PWM !PWM PWM !PWM
BA 1000 LOW HIGH PWM !PWM LOW LOW
BA_BC 1011 LOW HIGH PWM !PWM LOW HIGH
BC 1010 LOW LOW PWM !PWM LOW HIGH
BC_AC 0011 PWM !PWM PWM !PWM LOW HIGH
AC 0010 PWM !PWM LOW LOW LOW HIGH
AC_AB 0111 PWM !PWM LOW HIGH LOW HIGH
Align 1110 PWM !PWM LOW HIGH LOW HIGH
Stop 0000 LOW LOW LOW LOW LOW LOW

Table 5. 1-PWM Diode Freewheeling

STATE INLA:INHB:INLB:INHC GHA GLA GHB GLB GHC GLC
AB 0110 PWM LOW LOW HIGH LOW LOW
AB_CB 0101 PWM LOW LOW HIGH PWM LOW
CB 0100 LOW LOW LOW HIGH PWM LOW
CB_CA 1101 LOW HIGH LOW HIGH PWM LOW
CA 1100 LOW HIGH LOW LOW PWM LOW
CA_BA 1001 LOW HIGH PWM LOW PWM LOW
BA 1000 LOW HIGH PWM LOW LOW LOW
BA_BC 1011 LOW HIGH PWM LOW LOW HIGH
BC 1010 LOW LOW PWM LOW LOW HIGH
BC_AC 0011 PWM LOW PWM LOW LOW HIGH
AC 0010 PWM LOW LOW LOW LOW HIGH
AC_AB 0111 PWM LOW LOW HIGH LOW HIGH
Align 1110 PWM LOW LOW HIGH LOW HIGH
Stop 0000 LOW LOW LOW LOW LOW LOW